Performance IP Design Verification Lead
Core
Managing and guiding a team of engineers to ensure the functional verification of complex digital IP blocks for Flagship Smartphone/Compute SOCs.
Role type
Senior IC design verification lead (IP)
Builds
Flagship Smartphone/Compute System on Chips (SOCs)
Domain
Semiconductor / Digital IP / SoC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, formal verification, assertion-based methods, constrained-random environments, test plan creation, functional coverage analysis, team management, system architecture understanding
Technologies
SystemVerilog, UVM
Responsibilities
Build, mentor, and manage a team of design verification engineers; Collaborate with IP integrators to understand HW/SW requirements and create system checkers; Define and own verification methodologies including constrained-random environments and formal verification; Create and review test plans, write directed/random test cases, debug failures, and close functional and code coverage; Work with design teams to ensure full verification coverage; Maintain dashboards and drive process improvements.
Seniority
Senior, hands-on IC with leadership
