Senior Chip Design Verification Engineer
Core
Design and verify Phy Layer IP blocks for high-speed networking silicon chips, building reference models and simulating chip entities to meet performance requirements.
Role type
Senior IC chip design verification engineer (RTL Frontend ASIC)
Builds
Networking silicon chips (Phy Layer IP)
Domain
Semiconductor / Networking
Deliverable
production ML models | product features
Required skills
RTL Frontend ASIC Design, Chip Design Verification, Specman, Verilog, Debugging, Problem-solving, Analytical skills
Preferred skills
Knowledge in Specman, Knowledge in Verilog
Responsibilities
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements, collaborate with Architecture, Micro-Architecture, FW, and Post-Silicon validation teams
Seniority
Senior, hands-on IC
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