Senior IC Verification Engineer（MBJ）
Core
Developing and maintaining SoC/IP verification flows and participating in verification across different chip levels.
Role type
Senior IC verification engineer (SoC/IP)
Builds
RISC-V IP (CPU core, caches, coherency units) and SoC-level DFT designs
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, SystemVerilog, RISC-V architecture, DFT methodologies, ATPG, MBIST, LBIST, HSAT, formal verification, emulation, EDA tool development
Preferred skills
EDA vendor collaboration, industry-leading verification methodology promotion
Technologies
UVM, SystemVerilog, RISC-V, ATPG, MBIST, LBIST, HSAT
Responsibilities
Develop and maintain verification tools and flows; Verify RISC-V IP including CPU cores and cache subsystems; Perform SoC-level DFT design verification using simulation, formal, and emulation techniques
Seniority
Senior, hands-on IC
