Lead Product Engineer - Design Verification (MM/VIP)
Core
Lead Product Engineer driving adoption of Cadence's Memory Verification IP (VIP) portfolio for protocols like DDR5, GDDR6, and DFI, supporting pre-sales and customer design flows.
Role type
Senior IC product engineer (verification IP)
Builds
Memory Verification IP models and technical collateral for electronic design automation
Domain
Semiconductor EDA / Memory protocols
Deliverable
product features
Required skills
System Verilog, UVM methodology, Memory protocol expertise, DFI protocol knowledge, complex problem solving, technical specification translation
Preferred skills
DFI protocol deep expertise, cross-functional program leadership
Technologies
System Verilog, UVM, DDR5, GDDR6
Responsibilities
Lead high-complexity cross-functional programs, drive product knowledge transfer to customers and field engineers, translate customer requirements into technical specs, manage vendor issue resolution and roadmap influence
Seniority
Senior, hands-on IC
