Staff/Senior Staff Engineer - AMS Verification
Core
Design verification of next generation IP/SoCs with emphasis on verifying and signing off performance, power, and functionality using RNM models.
Role type
Staff/Senior Staff AMS Verification Engineer
Builds
Mixed-signal SoCs and subsystems for smart home, industrial IoT, and smart cities markets
Domain
VLSI, Analog/Mixed-Signal (AMS) electronics, Embedded Systems
Deliverable
production ML models | product features
Required skills
AMS simulation (Cadence/Synopsys/Mentor), Verilog HDL, Verilog-A, Verilog-AMS, SystemVerilog, UVM, analog circuit design, testbench architecture, verification planning, regression suite development, SPICE simulation, Perl/Python/Tcl scripting
Preferred skills
Mixed-signal SoC project leadership, behavioral modeling, PMIC/DC-DC converter knowledge, silicon evaluation, mentoring
Technologies
Cadence Virtuoso, SPICE, SystemVerilog, UVM, Perl, Python, Tcl
Responsibilities
Develop and execute top-level test cases, self-checking test benches, and regression suites; Verify block-level and chip-level functionality and performance; Develop and validate high-performance behavior models; Support silicon evaluation and compare measurement results with simulations
Seniority
Senior, hands-on IC