Senior DFT Engineer
Core
Design for Testability (DFT) architecture and implementation for automotive-grade System-on-Chips (SoCs) and microcontrollers, ensuring safety and security standards for logic and memory tests.
Role type
Senior IC DFT Design Engineer
Builds
Automotive microcontrollers (MCUs) and zonal microcontrollers for software-defined vehicles
Domain
Automotive electronics / SoC design
Deliverable
production ML models | product features | infrastructure
Required skills
DFT architecture definition, Scan Insertion, ATPG, Memory Test methodologies, Verilog/VHDL, Tcl/Perl/Python scripting, silicon bring-up and debugging, timing constraints, industry-standard DFT tools (Modus, Genus, Xcelium, Jasper)
Preferred skills
Automotive-grade SoC design experience, ISO 26262 Functional Safety compliance, power management techniques, low-power design principles
Technologies
Modus, Genus, Xcelium, Jasper, Verilog, VHDL, Tcl, Perl, Python
Responsibilities
Define and influence DFT architecture for subsystems and SoCs to achieve automotive-grade Safety and Security standards; Collaborate with IP, Systems, and Architecture teams to derive requirements and align DFT goals; Partner with Product and Test Engineering teams to understand test needs, debug issues, and optimize test costs; Work with cross-functional teams (RTL, DV, PD) to ensure high-quality and timely DFT implementation
Seniority
Senior, hands-on IC
