Principal Design Engineer
Core
Design Verification for interconnect IP, crafting verification plans, and ensuring coverage closure for highly complex and configurable designs.
Role type
Principal Design Verification Engineer (Interconnect IP)
Builds
Verified interconnect IP and subsystems
Domain
Semiconductor / Hardware Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Interconnects, NoCs, Design Verification fundamentals, Automated testbench development, Perl/Unix scripting, Coverage collection and closure
Preferred skills
Formal Verification, Gate Level Simulations
Technologies
System Verilog, UVM, Perl, Unix shell
Responsibilities
Design Verification for interconnect IP, Crafting verification plans and executing on those plans to verify highly complex and configurable designs, Responsible for coverage collection and closure, Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
Seniority
Senior, hands-on IC
