Lead Design Engineer
Core
Lead Design Engineer responsible for IP integration, verification, and release of Cadence's IP solutions for customers.
Role type
Senior IC IP Integration and Verification Engineer
Builds
IP solutions (PHY and controller sub-systems) for customers
Domain
Semiconductor / VLSI / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL integration, verification, Verilog, System Verilog, UVM, PCIe/CXL/IDE protocols, ASIC development flows (Lint/CDC/Synthesis/STA), debugging, flow setup
Preferred skills
IP development team experience, scripting knowledge
Technologies
Verilog, System Verilog, UVM, Genus, Lint, CDC, Synthesis, STA, PCIe, CXL, IDE
Responsibilities
Integrate and verify IP solutions, add new features to RTL, ensure clean customer configurations via verification regressions, support customers, ensure designs meet LINT and CDC guidelines, debug and setup new ASIC flows
Seniority
Senior, hands-on IC
