Lead Hardware Engineer - DFT IP R&D
Core
Developing cutting-edge Design-for-Testability (DFT) tools and IP for the MODUS software solution to achieve high coverage and reduced test time.
Role type
Lead Hardware Engineer - DFT IP R&D
Builds
DFT IP features, full scan, compressed/uncompressed scan, memory BIST, JTAG, IEEE 1500, and boundary scan at block and SoC levels
Domain
Electronic Design Automation (EDA) / Semiconductor / DFT
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design (Verilog, SystemVerilog), DFT architecture, verification (UVM), static timing analysis (STA), synthesis, data structures and algorithms, scripting (Perl, Python)
Preferred skills
DFT methodologies, EDA tool development concepts
Technologies
Verilog, SystemVerilog, UVM, Perl, Python
Responsibilities
Designing and verifying RTL and test benches for DFT IP features; Providing R&D support for problem analysis, debugging, and feature development to optimize synthesis results
Seniority
Senior, hands-on IC
