SoC Design Verification Engineer
Core
Deliver performant and functionally accurate silicon for high-performance GenAI products across compute, memory management, and high-speed connectivity.
Role type
Senior IC SoC Design Verification Engineer
Builds
High-performance silicon for GenAI models
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV), formal verification, simulated verification, silicon micro-architecture knowledge, high-speed connectivity, memory management
Preferred skills
emulation and prototyping platforms, silicon debug and bring-up
Technologies
SystemVerilog, Python, C/C++, Bluespec, UVM
Responsibilities
Contribute to scalable verification methodology across blocks, subsystems, and full-chip; Own verification execution at subsystem and chip-level creating testbenches and tests; Plan and drive reviews on verification test plans and closure towards silicon milestones
Seniority
Senior, hands-on IC
