DFT 高级工程师
Core
Designing and implementing SOC/IP DFT architectures, ATPG, and pattern simulation to ensure silicon testability.
Role type
Senior IC DFT Engineer
Builds
SOC/IP chips with robust test methodologies
Domain
Semiconductor / Digital SoC Design
Deliverable
production ML models | product features | infrastructure
Required skills
SOC/IP DFT architecture planning, ATPG development, pattern simulation, DFT implementation, silicon test diagnosis, in-house methodology development
Preferred skills
Advanced DFT design architecture research, flow development
Technologies
ATPG, pattern simulation tools, DFT flows
Responsibilities
Plan SOC/IP DFT architecture, research advanced DFT methods, develop new DFT flows, assist in solving DFT implementation and silicon test issues
Seniority
Senior, hands-on IC
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