Design Verification Engineer - Internal IP
Core
Develop and maintain UVM/SystemVerilog testbenches to validate custom IPs (systolic arrays, DMA engines, NoCs) for high-performance inference chips.
Role type
Design Verification Engineer (Internal IP)
Builds
Custom hardware IPs for AI inference workloads
Domain
Semiconductor / AI Infrastructure
Deliverable
production ML models
Required skills
UVM, SystemVerilog, digital design fundamentals, computer architecture, debugging complex datapaths
Preferred skills
SystemVerilog Assertions (SVA), formal verification, verifying systolic arrays/DMA/NoC/AXI, Python/Perl/TCL scripting
Technologies
UVM, SystemVerilog, Python, Perl, TCL
Responsibilities
Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs; Define and execute verification plans covering functional correctness and performance; Debug complex datapath and protocol issues; Partner with SW, FW, and emulation teams for end-to-end bring-up; Contribute to reusable DV infrastructure and coverage models
Seniority
Mid-Senior, hands-on IC
