Principal Design Engineer
Core
Design Verification Engineer for Serial and Interface Design IPs (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C) within the IP development team.
Role type
Principal Design Engineer (Verification)
Builds
Robust, scalable, and efficient UVM testbenches and verification strategies for complex design IPs.
Domain
Electronic Design Automation (EDA) / Semiconductor IP / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM testbench development, Formal verification, Emulation qualification, Verification strategy planning, Debugging, Analytical problem solving
Preferred skills
Self-starter mindset, Time management, Quality focus
Technologies
UVM, Formal verification tools, Emulation platforms, PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C
Responsibilities
Develop UVM testbenches to verify design IPs; Participate in Formal verification of complex design modules; Engage in Emulation qualification of design IPs; Understand design specifications and produce detailed verification strategies and test plans.
Seniority
Principal, hands-on IC
