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Software Engineering
› Hardware Verification
Hardware Verification
1,141 open positions
CAD Flow Automation and AI Engineer
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Apple
Sunnyvale, CA, US
$150k–$278k
6mo
Enhance and maintain automation systems for analysis/QA and existing AI applications serving CAD and design teams while driving innovation through frontier technology projects.
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Physical Design Backend STA Engineer
NVIDIA
Israel, Yokneam
6mo
Perform advanced Static Timing Analysis (STA) at chiplet and FC level to ensure timing convergence and quality approval for high-speed communication devices.
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Senior DFT Consultant (Tessent)
Siemens-Eda
Remote
$147k–$293k
6mo
Design for Test Consultant supporting the use of Tessent DFT software in the design of complex ASIC designs, implementing and verifying DFT features for enterprise customers.
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GenAI Physical Synthesis Engineer
Apple
Santa Clara, United States of America
6mo
Develop GenAI-powered agentic applications to automate and optimize RTL-to-GDS physical synthesis flows for Apple processors and SoCs.
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CAD Engineer - Circuit Simulation Methodology
Apple
Austin, United States of America
6mo
Developing and refining custom transistor-level simulation and EM/IR analysis methodologies to support scalable circuit verification solutions.
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Software Intern
Cadence
SAN JOSE
6mo
Software intern role focused on research and development of on-chip in parasitic modeling using state-of-the-art machine learning technologies.
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Senior/Staff Engineer, Frontend Labor Productivity & Data Engineering
Micron
Hiroshima - Fab 15, Japan
6mo
Drive measurable outcomes in labor productivity and annualized hour savings by implementing strategies focused on standardization, simplification, automation, and leveraging generative AI methodologies.
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Principal/Senior Principal Engineer – Arm ARM
Arm
Cambridge, United Kingdom
6mo
Lead the delivery and evolution of the Arm Architecture Reference Manual (Arm ARM), ensuring architectural intent is accurately communicated and the product maintains high quality, correctness, and accessibility.
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CAD Flow Automation and AI Engineer
Apple
Sunnyvale, United States of America
6mo
Design and manufacture next-generation, high-performance, power-efficient processor and system-on-chip (SoC) for Apple devices.
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Virtuoso Custom CAD Engineer
Apple
Beaverton, United States of America
6mo
Provide engineering support for digital, analog, and mixed-signal IC designs using Cadence tools to enable Apple's high-performance display and image sensors.
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Package Development Engineering – Product Integration Engineer (PDE PIE)
Micron
MSB, Singapore
7mo
Integrate AI-assisted tools into daily work, drive New Product Introduction (NPI) processes, and act as a technical integrator across manufacturing sites to bring new semiconductor packages into volume production.
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Engineer, Process Development (Core Engineering Module)
Micron
MSB, Singapore
7mo
Engineer responsible for integrating AI tools into daily work, executing NPI product qualifications, and leading continuous improvement of assembly processes to ensure high yield and cost efficiency in semiconductor manufacturing.
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Package Development Engineering – Product Integration Engineer (PDE PIE)
Micron
Singapore, Singapore
7mo
Integrate AI tools into daily work, drive New Product Introduction (NPI) processes, and act as a technical integrator across manufacturing sites to bring new semiconductor packages into volume production.
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Principal EDA Software Engineer (C++, Characterization)
Cadence
SAN JOSE
$137k
7mo
Develop and enhance transistor-level analysis tools for static and dynamic circuit characterization, enabling timing, power, noise, and reliability analysis for advanced custom digital and mixed-signal circuits.
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DFT Intern
Etched
San Jose
7mo
Review and refine DFT flow automation to support chip-level regression on Caelius, contributing to DFT verification and developing flows for ATPG fault models.
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Software Engineer - Platform Technologies
SiFive
Austin, Texas, United States
7mo
Develop and maintain core tools and flows for microprocessor design, including simulation and build tools to validate designs.
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Senior RTL Design Engineer - CPU Frontend
SiFive
Santa Clara, California, United States
$159k
7mo
Architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
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Design Verification Infrastructure Engineer - Software
SiFive
Hsinchu, Taiwan
7mo
Develop and maintain the Verification Platform libraries and tools used across SiFive for Design Verification and validation activities.
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Analog EDA Backend Lead
Texas Instruments
Bengaluru, Karnataka, India
7mo
Lead EDA solutions development, vendor tool evaluation, and PDK usage support for TI's internal and external design teams.
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Physical Design Engineer, Machine Learning
Apple
San Jose, United States of America
7mo
Designing predictive models, optimization algorithms, and autonomous agents to optimize Power, Performance, and Area (PPA) for System-on-Chip (SoC) physical design.
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Senior Integration/API architect
PsiQuantum
Palo Alto, California, United States
7mo
Design and scale the integration architecture connecting photonic IC, passive, and active IC design toolchains for a silicon photonic quantum computer.
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CAE電腦輔助自動化軟體工程師 (林口園區)
AdvanTech
Linkou
7mo
Responsibilities: Develop PCB Layout automation processes using SKILL language in Cadence EDA Tool to replace manual tasks; Build automated program editing architecture using AI technology; Develop and maintain Layout management system using PHP.
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Engineer, Product & System Engineering (Media Health Reliability), Heteregenous Integration - High Bandwidth Memory
Micron
Fab 10A, Singapore
7mo
Drive intrinsic and extrinsic reliability test development and execution for High Bandwidth Memory (HBM) products, focusing on DPM reduction and root cause analysis for defectivity and reliability failures.
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Photonic IC Development Tech Lead
MediaTek
San Jose, CA
7mo
Leading the end-to-end development and design platform for high-volume silicon photonics integrated circuits (PICs), establishing methodology for device design, integration, and production ramp.
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Staff Digital Design Engineer
ON Semiconductor
Bangalore, Karnataka, India
7mo
Designing and verifying digital processing blocks for CMOS Image Sensors used in automotive and industrial applications.
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IC Software Development Senior Engineer/Technical Manager
MediaTek
HsinChu
7mo
Lead software development for IC (Integrated Circuit) projects, including feature implementation and validation.
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Design Engineering Architect — Memory Modeling Portfolio
Cadence
GYEONGGI-DO (Seoul)
7mo
Senior technical anchor and customer-facing expert for memory protocol IP (UFS/Unipro/MPHY/RMMI) at Cadence, bridging deep protocol knowledge with direct customer partnership to debug, integrate, and deploy complex memory solutions.
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Senior AI and LLM Solutions Software Engineer
NVIDIA
Israel, Yokneam
7mo
Develop AI, Machine Learning (ML), and Large Language Models (LLMs) based solutions to enhance chip design and verification workflows.
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Computing System Architecture Engineer (Benchmark Optimization)
MediaTek
HsinChu
7mo
Analyze benchmarks to identify performance and power bottlenecks, build system models for SoC optimization, and propose actionable system-level improvement strategies.
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HSI SW / System development engineer
MediaTek
HsinChu
7mo
Design and validation of HSI system software (drivers/firmware) and hardware (PCB/PHY) for interfaces including USB, PCIe, MIPI, UFS, DP, and HDMI.
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Front-End Power Engineer
Etchedai
Hardware Engineering
7mo
Optimizing RTL designs and power efficiency for AI chips (ASICs) to support high-throughput, low-latency model architectures like transformers.
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Front-End CAD Engineer
Etchedai
Hardware Engineering
7mo
Building and maintaining front-end IC design flows, verification toolchains, and project execution dashboards for AI chip development.
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Emulation Software Engineer
Etchedai
Software Engineering
7mo
Building high-performance emulation software and tooling to accelerate pre-silicon validation of AI chips (ASICs) designed for specific model architectures like transformers.
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Digital Design Member of Technical Staff (MTS)
ON Semiconductor
Cork, Co. Cork, Ireland
7mo
Architecting, designing, and integrating complex digital controller IP for power, clock, and error management subsystems within automotive-grade SoCs.
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Lead Software Engineer - AI/LLM for Virtuoso
Cadence
BEIJING
7mo
Designing, implementing, and maintaining software features and interfaces for the Cadence Virtuoso platform to integrate emerging Agentic AI frameworks into electronic design automation tools.
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Senior Principal Software Engineer - Accelerated Verification IP
Cadence
SAN JOSE
$154k
7mo
Designing, developing, and maintaining PCIe/CXL Accelerated Verification IP (AVIP) and Virtual Bridge (VB) components for high-performance emulation and system verification.
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Senior Software Engineer, Embedded Algorithm Verification & Automation
Analogdevices
India, Bangalore, Nova
7mo
Automate validation of measurement and monitoring algorithms for power systems and data center infrastructure.
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DFM RET Engineer
Texas Instruments
Dallas, TX, United States
7mo
Develop and deploy Optical Proximity Correction (OPC) models and Design for Manufacturability (DFM) solutions to ensure accurate printing of chip designs at 28nm and below.
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Principal DV Engineer
MediaTek
San Jose, CA
7mo
Lead verification engineering for a high-end CPU project, focusing on testbench architecture, stimulus generation, and bug triage.
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Performance Modeling Engineer
MediaTek
San Jose, CA
7mo
Develop performance modeling methodologies and simulation infrastructure to support CPU and SoC architectural exploration and microarchitectural trade-off decisions.
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Technical Leader DFT & STA
Cisco
Armenia
7mo
Developing innovative Physical Design methodologies and robust flows for complex ASIC chips, focusing on DFT Timing Engineering and Static Timing Analysis (STA) in test modes.
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ICE Graduate Talent
Intel
Malaysia, Penang
7mo
Entry-level program for fresh graduates and early career professionals to join Intel's engineering and technical teams in Malaysia.
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CAD Support - Student
Altera
TLV, IL
8mo
Supporting and stabilizing EDA tools and version management systems for global teams developing high-speed communication devices.
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Staff/Senior Engineer -Package Health System and Analytics
Micron
Fab 10A, Singapore
8mo
Develop and execute package health monitoring, simulation, and characterization activities to ensure robust semiconductor packaging solutions.
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Senior C++ Software Engineer (Leading-Edge, High-Performance R&D solutions) - Hybrid model, Shannon.
Siemens-Eda
Shannon, IRL, Ireland
€68k
8mo
Design, develop, and optimize high-performance, production-ready components for next-generation Electronic Design Automation (EDA) applications, focusing on distributed systems and low-latency operations.
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CAD Engineer
NVIDIA
India, Bengaluru
8mo
Architecting and developing end-to-end EDA tool flows to auto-generate system fabrics, sub-systems, and SOC hierarchies for chip designers.
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Senior/Staff/Principal - Adv Pkg TD Integrator
Micron
Fab 10A, Singapore
8mo
Developing advanced packaging process solutions to ensure success for new processes, equipment, materials, and pathfinding activities for all advanced packaging products.
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Mixed-Signal Digital IC Design Engineer(Serdes, High Speed Interface)
MediaTek
HsinChu
8mo
Architecting, coding, and integrating Serdes/High Speed Interface PHYD IP for digital logic and analog co-simulation.
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High-speed transmission interface IP development software/firmware engineer
MediaTek
ChuPei
8mo
Design and develop IP drivers, software system architectures, and AI-assisted design flows for high-speed SerDes communication interfaces.
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Manufacturing Equipment Technician - Backend
ON Semiconductor
Mountain Top, PA, United States
$5k
8mo
Maintain and troubleshoot semiconductor manufacturing equipment including ion implant, metals sputter deposition, wafer thinning, and probe test systems.
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