Technical Leader DFT & STA
Core
Developing innovative Physical Design methodologies and robust flows for complex ASIC chips, focusing on DFT Timing Engineering and Static Timing Analysis (STA) in test modes.
Role type
Senior IC DFT Timing Engineer (Physical Design)
Builds
Complex ASIC chips for Cisco's silicon architecture
Domain
Semiconductor / ASIC Design / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA), SDC development (block/sub-chip/full-chip), timing constraints management, Perl/TCL/Python/Makefile scripting, test mode analysis (scan shift/capture/ATPG)
Preferred skills
Timing closure for DFT modes (scan shift/capture/BIST), SDC debugging, Synopsys Fusion Compiler usage, Tessent tool for DFT insertion, RTL-level DFT insertion
Technologies
PrimeTime, Synopsys GCA/TCM, Synopsys Fusion Compiler, Tessent
Responsibilities
Develop timing constraints at block, sub-chip, and full-chip levels in test modes; perform quality checks on duplicated constraints and promotion/demotion between block and top level SDCs; check timing for unconstrained endpoints and no-clock scenarios; develop methodologies, guidelines, and checklists to streamline STA work and resolve design/flow issues
Seniority
Senior, hands-on IC
