DFT Intern
Core
Review and refine DFT flow automation to support chip-level regression on Caelius, contributing to DFT verification and developing flows for ATPG fault models.
Role type
DFT Intern
Builds
DFT flow automation and verification flows for chip-level regression
Domain
Semiconductor hardware design / AI infrastructure
Deliverable
production ML models
Required skills
Hardware description languages (Verilog, SystemVerilog), Digital logic design fundamentals, ASIC design flow knowledge (synthesis, STA, DFT), Scripting (Python, Tcl), Learning modern AI concepts (transformers)
Preferred skills
DFT concepts (MBIST, scan insertion, scan compression), DFT tooling (Tessent), ATPG fault models (SAF, TDF, BDF, IDDQ, PDF), DFT flow automation experience, Clocking and reset schemes
Technologies
Caelius, Tessent, Python, Tcl, Verilog, SystemVerilog
Responsibilities
Review and refine DFT flow automation, Contribute to DFT verification (MBIST, Scan, BSCAN, SSN simulations), Develop flows for various ATPG fault models
Seniority
Intern
