Principal DV Engineer
Core
Lead verification engineering for a high-end CPU project, focusing on testbench architecture, stimulus generation, and bug triage.
Role type
Principal Digital Verification Engineer (CPU)
Builds
In-house Built-in Function Models (BFMs), unit-level testbenches, and verification environments.
Domain
Semiconductor / CPU Design / Digital Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM methodology, testbench architecture, assertion/coverage development, directed and random testcase generation, bug triage, functional coverage analysis
Preferred skills
Core-level verification, stimulus creation
Technologies
UVM, SystemVerilog (implied by UVM context), CPU architecture
Responsibilities
Architect and implement UVM-based testbenches and components; Build in-house BFMs and unit-level testbenches; Create testplans and implement checkers/assertions/coverages; Drive directed and controlled random testcases; Triage bug reports and profile failure cases.
Seniority
Principal, hands-on IC
