Design Engineering Architect — Memory Modeling Portfolio
Core
Senior technical anchor and customer-facing expert for memory protocol IP (UFS/Unipro/MPHY/RMMI) at Cadence, bridging deep protocol knowledge with direct customer partnership to debug, integrate, and deploy complex memory solutions.
Role type
Senior Design Engineering Architect (Memory Modeling)
Builds
Memory model IP library and hardware emulation solutions for hyperscale, AI, mobile, automotive, and defense/aerospace customers.
Domain
Semiconductor hardware emulation, memory protocols (UFS, Unipro, MPHY, RMMI, SDRAM, NAND Flash), and system-level debugging.
Deliverable
Production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UFS/Unipro/MPHY/RMMI protocol stack expertise, SystemVerilog/Verilog RTL design and verification, hardware emulation debugging, system-level problem definition, technical mentoring, cross-functional collaboration
Preferred skills
Cadence Palladium/Protium platform experience, scripting (Perl/TCL/C-shell), broader memory protocol knowledge (SDRAM/NAND), cross-cultural relationship building
Technologies
Cadence Palladium, Cadence Protium, SystemVerilog, Verilog, UFS, Unipro, MPHY, RMMI, DDRx, LPDDRx, HBMx, NAND Flash, DFI PHY
Responsibilities
Serve as primary Korea-based customer interface for protocol integration and solutions consulting; debug and characterize customer issues to define root causes; triage field issues and coordinate model defect repairs; map customer requirements to product capabilities; mentor engineers on protocols and verification; review RTL implementation approaches; partner with global teams for customer success
Seniority
Senior, hands-on IC with mentorship responsibilities
