Senior RTL Design Engineer - CPU Frontend
Core
Architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
Role type
Senior IC CPU Frontend Design Engineer
Builds
RISC-V CPU cores and core generators
Domain
Semiconductor / CPU Design / RISC-V
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
CPU RTL design, Verilog, System Verilog, VHDL, functional programming, templated metaprogramming, compiler infrastructures, data modeling, test-driven development
Preferred skills
Scala/Chisel, Bluespec, RISC-V architecture, UVM, Git/Github, Jira, Confluence
Technologies
Chisel, FIRRTL, Verilog, System Verilog, VHDL, Scala, Bluespec, UVM, Git, Github, Jira, Confluence
Responsibilities
Architect and implement new features and ISA extensions in RISC-V CPU core generators; Integrate design content into Chisel/FIRRTL framework; Perform initial sandbox verification and create verification test plans; Collaborate with physical implementation team for optimization; Work with performance modeling team for optimization; Develop microarchitecture and specification
Seniority
Senior, hands-on IC
