DFM RET Engineer
Core
Develop and deploy Optical Proximity Correction (OPC) models and Design for Manufacturability (DFM) solutions to ensure accurate printing of chip designs at 28nm and below.
Role type
Senior IC computational lithography engineer (OPC/DFM)
Builds
Production-ready analog and embedded processing chips for Texas Instruments
Domain
Semiconductor manufacturing, advanced node lithography (28nm)
Deliverable
production ML models | product features
Required skills
Optical lithography principles, RET (OPC, SRA, assist features), industry-standard OPC tools (Synopsys Sentaurus Lithography, Siemens EDA Calibre, ASML Brion), scripting (Python, TCL, Perl), DFM analysis, root cause analysis of patterning defects, automation script development
Preferred skills
Analog layout interaction with lithography, layout tools (Cadence Virtuoso), DRC and LVS, machine learning or AI techniques for OPC/DFM
Technologies
Synopsys Sentaurus Lithography, Siemens EDA Calibre, ASML Brion, Python, TCL, Perl, Cadence Virtuoso
Responsibilities
Develop, evaluate, and implement advanced OPC models and recipes for 28nm technologies; Perform comprehensive DFM analysis on product designs to identify and mitigate manufacturing issues; Collaborate with design teams to define DFM guidelines and ensure layout compliance; Work with lithography and process engineering teams to optimize OPC recipes and improve patterning performance; Interface with OPC and lithography engineers to co-optimize layout structures for printability; Analyze lithography process data and wafer yield data to identify root causes of patterning defects; Develop and maintain automation scripts for OPC/DFM flows
Seniority
Senior, hands-on IC