Senior Principal Software Engineer - Accelerated Verification IP
Core
Designing, developing, and maintaining PCIe/CXL Accelerated Verification IP (AVIP) and Virtual Bridge (VB) components for high-performance emulation and system verification.
Role type
Senior Principal Software Engineer (Protocol Verification)
Builds
High-performance protocol solutions for Palladium and Protium emulation platforms
Domain
Semiconductor verification, hardware/software co-design, interconnect protocols
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital design fundamentals, computer architecture, SystemVerilog/Verilog, C/C++, PCIe protocol knowledge, CXL protocol knowledge, hardware description languages, emulation flows, debugging with waveforms/logs
Preferred skills
NVMe protocol knowledge, hybrid verification flows, system-level verification
Technologies
SystemVerilog, Verilog, C, C++, PCIe, CXL, NVMe, Palladium, Protium
Responsibilities
Designing and implementing protocol functionality in AVIP/VB components, developing and debugging BFMs/transactors, ensuring correctness and scalability in emulation flows, collaborating with cross-functional teams, participating in feature bring-up and release activities, supporting customer issues and delivering fixes
Seniority
Senior, hands-on IC
