Physical Design Backend STA Engineer
Core
Perform advanced Static Timing Analysis (STA) at chiplet and FC level to ensure timing convergence and quality approval for high-speed communication devices.
Role type
Senior IC physical design STA engineer
Builds
High-speed networking chips (chiplets and FC level)
Domain
Semiconductor / Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA), Prime Time tool usage, SDC generation, timing path debugging, constraint analysis, chiplet design, full timing closer
Preferred skills
Physical build flows, PNR, physical verification
Technologies
Prime Time
Responsibilities
Perform advanced STA at chiplet and FC level, review and debug timing paths, identify convergence risks, work with physical design/RTL/DFT teams, ensure full timing closer and quality approval
Seniority
Mid-level, hands-on IC
