Front-End Power Engineer
Core
Optimizing RTL designs and power efficiency for AI chips (ASICs) to support high-throughput, low-latency model architectures like transformers.
Role type
Senior IC physical design engineer (power optimization)
Builds
Custom AI ASICs (e.g., Sohu) for real-time video generation and deep reasoning agents
Domain
Semiconductor hardware design / AI infrastructure
Deliverable
production ML models
Required skills
RTL development (Verilog/SystemVerilog), low-power design techniques (clock gating, power gating, DVFS), synthesis and place-and-route optimization, power estimation and PPA trade-off analysis
Preferred skills
UPF/CPF power intent specifications, power analysis tools (Synopsys PrimePower, Cadence Joules), workflow automation (Tcl, Perl, Python)
Technologies
Verilog, SystemVerilog, UPF, CPF, Synopsys PrimePower, Cadence Joules, Tcl, Perl, Python
Responsibilities
Optimize RTL designs for power efficiency while meeting performance and area objectives; Perform power analysis across silicon design stages; Conduct power estimation and evaluate PPA trade-offs; Collaborate with physical design teams during synthesis, place-and-route, and sign-off phases; Create precise power models from RTL simulations and gate-level netlists
Seniority
Senior, hands-on IC
