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Software Engineering
› Hardware Verification
Hardware Verification
799 open positions
ENGINEER - PLN STRATEGIC LAYOUT
Micron
Fab 10N/X, Singapore
2mo
Optimize production equipment layouts in semiconductor fabs to improve material flow, footprint efficiency, and factory output using industrial engineering principles.
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Principal Member of the Technical Staff - IP Engineering
GlobalFoundries
Hsinchu
2mo
Lead or co-lead the development of high-performance compute processor IP products, providing technical leadership across product development, customer engagements, and strategic initiatives.
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Application Support Engineer
Siemens-Eda
Bangalore, IND, India
2mo
Provide frontline technical support for EDA software/tools, resolving customer queries and bridging the gap between software solutions and customer needs.
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Digital Design Verification Trainee
Semtech
MEX - Aguascalientes
2mo
Functional verification of high-speed digital circuits and behavioral modeling of analog/mixed-signal circuits within mixed-signal ICs for data communications and video broadcast.
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Intern - PEE DIFFUSION
Micron
Fab 10N/X, Singapore
2mo
Driving yield improvement initiatives through CMOS matching analysis and Wafer Edge Exclusion (WEE) program to reduce inline mismatches and edge-related yield loss.
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Software Engineer (Circuit Analysis, EDA frameworks, AI agents)
Cadence
PORT MOODY 01 (VANCOUVER)
$90k–$166k
2mo
Designing, implementing, and maintaining software for transistor-level electrical circuit simulation within emerging Agentic AI frameworks for electronic design automation.
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Staff Design Engineer - SOC
Silabs
Singapore
2mo
Designing digital blocks and SoC infrastructure for low-power mixed-signal SoCs in wireless connectivity products.
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Senior Software Engineer- C++
Siemens-Eda
Noida, IND, India
2mo
Design and develop new simulation engines and core algorithmic advances for the QuestaSim R&D platform to enable faster electronic product development.
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Fronted End Central Process Integration Engineer/Senior Engineer
Micron
Fab 10A, Singapore
2mo
Design, execute, and analyze experiments to improve fab process, yield, and quality for memory and storage products.
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Functional Verification Agentic AI focused - Application Engineer
Siemens-Eda
Santa Clara, CA, United States
$147k–$147k
2mo
Drive and grow Agentic AI business across Americas accounts by acting as a liaison between Functional Verification AI experts and customer technical owners to uncover, shape, and deploy AI solutions in design and verification flows.
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Frontend Central Product Integration Engineering (cPIE) AI Transformation Skill Management Engineer
Micron
Singapore, Singapore
2mo
Drive convergence of AI and semiconductor manufacturing excellence by leading AI-powered innovation in process capability, yield optimization, and quality improvement while owning the lifecycle of AI agents that automate engineering workflows.
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Industrial Engineer, US Front-End Expansion Planning
Micron
Boise, ID - ID1
2mo
Planning capital impacts and optimizing capacity for new high-volume memory manufacturing facilities in the US.
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Software Engineer
Siemens-Eda
Austin, TX, United States
$74k–$74k
2mo
Develop cutting-edge algorithms and software design/architecture for industry-leading simulation tools used in chip, board, and system design.
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SOC Frontend Integration Engineer
Altera
Penang 15, Penang, Malaysia
2mo
Constructing top-level System-on-Chip (SoC) RTL integration by assembling internal and third-party IPs into complex FPGA designs.
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Staff Engineer, Research Science Engineering
Analogdevices
2 Locations
2mo
Research, develop, and support software tools for modeling, simulating, and designing analog/mixed-signal integrated circuits (ICs) to enable IC designers.
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Software Engineer II: Jasper R&D
Cadence
BELO HORIZONTE
2mo
Developing and validating enhancements on the Jasper Graphical User Interface, specifically the Visualize™ waveform viewer, to push boundaries in verification debug capabilities.
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Senior Design Automation Engineer, Applied AI
NVIDIA
US, CA, Santa Clara
$196k–$196k
2mo
Lead end-to-end solution development for AI-driven timing and constraint analysis workflows in semiconductor design automation.
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Senior Information Developer (Technical Author)
Arm
Cambridge, United Kingdom
2mo
Define how users discover, understand, and adopt telemetry capabilities by bringing together content strategy, architecture, user experience, and tooling into a cohesive vision for Arm's developer experience.
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D&E - Virtual Compute Platform (VCP) Software Engineering Manager - Linkou
ASML
Linkou, Taiwan
2mo
Lead end-to-end engineering delivery for the Virtual Compute Platform (VCP) submodule, ensuring high-quality execution and 99.99% uptime for analytics applications in semiconductor factories.
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Field Application Engineer - Tessent Design for Test (DFT)
Siemens-Eda
Santa Clara, CA, United States
$147k–$293k
2mo
Drive Siemens Tessent DFT products into customer projects by creating methodologies, integrating flows, and debugging bring-up processes to support sales campaigns.
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R&D Senior Architect, Package Substrate EDA
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Synopsys
Remote
$251k–$251k
2mo
Architecting next-generation package substrate design automation tools for the semiconductor industry, focusing on physical design, auto routing, and power integrity.
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Global Front End Planning: Strategic Operations Engineer
Micron
Fab 10A, Singapore
2mo
Lead scenario studies and strategic operations for semiconductor manufacturing, aligning product roadmaps with business goals to optimize capacity, cost, and market share.
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Global Front End Planning: Strategic Operations Engineer
Micron
Singapore, Singapore
2mo
Lead scenario studies and strategic operations for semiconductor manufacturing, optimizing fab capacity, production planning, and business alignment to support DRAM, NAND, and NOR memory product roadmaps.
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Staff Applications Engineer (Debug)
Arm
Multiple locations
2mo
Guide partners through complex software technical challenges involving debug, development tools, and debug probes, while supporting hardware bring-up and SoC issues.
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Machine Learning and Optimization Engineer
Samsung Electronics
12100 Samsung Blvd, Austin, TX, USA
$76k–$76k
2mo
Developing and refining machine learning models for large-scale forecasting and optimization of semiconductor manufacturing line performance.
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Hardware and Software Engineer FPGA / HPC – Real-Time Simulation / Compiler Building (f/m/d)
Digsilent GMBH
Remote
3mo
Research and development of numerical solvers and compiler techniques for real-time simulation of power systems and power electronics on FPGA/CPU hybrid platforms.
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Member of Technical Staff - Drive Qual
Purestorage
Office - India (Bangalore - Prestige Dynasty Phase 2)
3mo
Ensure performance and reliability of SSDs for hyperscale and enterprise environments through rigorous system-level testing and data-driven analysis.
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Engineer for new coater/developer at TAK
Lumentum
Japan - Tokyo (Takao)
3mo
Develops and introduces new InP-based Lithography processes and equipment for semiconductor manufacturing, defining exposure conditions and handling specifications to enable mass-production capacity ramp.
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Front End Central Product Integration (FE cPIE) Principal Engineer
Micron
Taoyuan - Fab 11, Taiwan
3mo
Provide leadership to the global Micron network to drive leading edge HBM Product yield, quality improvement, and new product introduction through technical expertise and project execution.
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Software Development Engineer
Siemens-Eda
Bangalore, IND, India
3mo
Developing efficient algorithms and implementing them for Analog FastSPICE™, a nanometer-accurate circuit verification platform used by semiconductor companies.
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Senior Engineer, Design Verification Engineering
Analogdevices
3 Locations
3mo
Develop and own verification for key digital blocks in mixed-signal SOCs for consumer audio products like hearables and prosumer audio.
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Sr. EDA Tools Engineer - PERC ESD
Intel
US, Oregon, Hillsboro
$150k–$150k
3mo
Develop PERC ESD rule decks and reliability design rule methodologies for Intel's latest process technologies to enable faster time-to-market for design teams.
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Certified Trainer and Content Developer
Renesas-Electronics
Tokyo, Tokyo, jp
3mo
Create and deliver technical training content and instruction for Altium's electronic design automation products to enable customer proficiency.
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Software Engineer II , Synthesis
Cadence
SAN JOSE
$102k–$102k
3mo
Design, develop, troubleshoot, debug, and support the Genus Synthesis Solution software for logic synthesis and physical design.
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系统集成工程师
Sicarrier
China / Guangdong-Shenzhen,China / Shanghai-Shanghai,China / Beijing-Beijing,China / Hubei-Wuhan,China / Jilin-Changchun
3mo
Design system solutions and models for high-precision equipment, perform integration verification, and debug system performance.
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Staff Digital Design Engineer, HBM
Micron
Richardson, TX
3mo
Designing high-performance digital logic blocks for advanced HBM memory products, translating specifications into robust RTL and optimizing for power, performance, and area.
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Principal SoC Integration Flow Architect - Automation
MediaTek
San Jose, CA
3mo
Architecting and developing a highly automated framework to streamline the path from IP handoff to full-chip netlist generation.
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Staff Architecture Formal Engineer
Arm
Cambridge, United Kingdom
3mo
Developing lightweight verification methods augmented with AI to check architectural properties and improve the Arm Architecture Specification Language.
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Applications Engineering Consultant - Emulation
Siemens-Eda
San Diego, CA, United States
$147k–$147k
3mo
Provide technical selling support and deploy emulation solutions for the Americas sales team, assisting in product evaluations and deployments for electronics and semiconductor companies.
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Field Application Engineer
Siemens-Eda
New Cairo, EGY, Egypt
$24k–$24k
3mo
Support business growth and technical execution for Electronic Design Automation software through customer engagement, sales campaign support, and technical demonstrations.
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Intership: Enable Agentic solutions (AI) on Validation field
Stmicroelectronics
Cornaredo, Italy
3mo
Design and implement a new cloud-based software system using AI technologies to support the validation of innovative electronic devices.
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Fellow, AI Systems Architect for Operations
Arm
Multiple locations
$309k–$309k
3mo
Define and implement large-scale autonomous AI systems spanning pre-silicon build, verification, Product & Test Engineering, Quality, Reliability, Product Operations, and Supply Chain Management to accelerate semiconductor product development.
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算法技术工程师
Sicarrier
China / Guangdong-Shenzhen,China / Shanghai-Shanghai,China / Beijing-Beijing,China / Hubei-Wuhan,China / Zhejiang-Hangzhou,China / Jilin-Changchun
3mo
Design and develop optical, thermal, positioning, error control, calibration, and fault diagnosis algorithms for semiconductor advanced process manufacturing, including mathematical modeling, system simulation, and hardware optimization.
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Principal AI Forward Deployment Engineer
Cadence
HOME OR, US
3mo
Embed with strategic semiconductor customers to operationalize Cadence's AI and agentic solutions across end-to-end silicon design flows, translating workflows into productivity wins.
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Software Developer - C++ *
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Siemens
Saskatoon, SK, CA
3mo
Develop advanced semiconductor design software (EDA) and AI-driven tools for chip design and manufacturing.
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算法技术工程师
Sicarrier
China / Guangdong-Shenzhen,China / Shanghai-Shanghai,China / Beijing-Beijing,China / Hubei-Wuhan,China / Zhejiang-Hangzhou,China / Jilin-Changchun
3mo
Design and develop optical, thermal, positioning, error control, calibration, and fault diagnosis algorithms for semiconductor advanced process manufacturing, including mathematical modeling, system simulation, and hardware optimization.
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Machine Vision & AOI Sr/Engineer
Micron
Taichung - MTB, Taiwan
3mo
Design, develop, and deploy camera-based automated optical inspection (AOI) systems for advanced packaging and manufacturing to improve defect detection, process control, and yield.
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Design Lead/ Front-End Architect / Datapath Lead
Lumilens
San Jose
3mo
Define digital front-end micro-architecture and own the high-speed datapath for a first-of-its-kind chiplet, serving as the architectural center connecting UCIe, in-house IP, and the optical engine.
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Lead Design Engineer
Cadence
BANGALORE
3mo
Lead verification strategy, architecture, and execution for semiconductor/ASIC/SoC designs, ensuring functional and timing sign-off.
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Senior/Staff Product Development
Micron
Hyderabad, Telangana, India
3mo
Develop test flows, strategies, and solutions for Micron's 3D NAND memory test chips, focusing on pre-si simulation, post-si validation, and failure analysis.
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