Senior Principal Software Engineer
Core
Architect and enhance the Xcelium RTL/logic simulator engine and Timing Constraints Verification technology for future AI and hyperscale chip designs.
Role type
Senior Principal Software Engineer (EDA/Logic Simulation)
Builds
Next-generation hardware verification technology (Xcelium simulator)
Domain
Semiconductor EDA, Logic Simulation, Timing Analysis
Deliverable
production ML models | product features
Required skills
C/C++, SystemVerilog, Verilog, graph algorithms, multi-threaded programming, performance optimization, SDC constraints, path exceptions handling
Preferred skills
RTL/logic simulation software development experience
Technologies
Xcelium, C/C++, SystemVerilog, Verilog
Responsibilities
Enhance and support Xcelium RTL/logic simulator engine; Design and tune graph algorithms for SDC constraints on multi-billion-node graphs; Conduct bottleneck analysis and implement performance optimizations; Write specifications and unit tests.
Seniority
Senior, hands-on IC
