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Software Engineering
› Hardware Verification
Hardware Verification
1,136 open positions
Senior Software Engineer
AMD
USA
1mo
Develop and improve FPGA device modeling and physical database software, applying data-driven approaches to optimization and participating in hardware bring-ups.
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Senior Computational Scientist / Software Engineer - Feature Scale Process Simulation
Lamresearch
US-MA-Waltham (1037)
1mo
Develop advanced feature-scale simulation software to predict nanoscale semiconductor structure evolution during plasma etch and deposition processes.
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Processor Design Verification Engineer
Qualcomm
San Diego, California, United States of America
1mo
Oversees architecture, design, verification, and performance analysis for Digital Signal Processor (DSP) development for Qualcomm Mobile, Machine Learning, Automotive, IoT, and other products.
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Quantum Qubit Design Engineer
Intel
US, Oregon, Hillsboro
1mo
Design and scale silicon-based spin qubit processors from initial conception through tapeout and fab integration, focusing on process-design-kit (PDK) definition, routing automation, and signal integrity for large-scale quantum chips.
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ASIC Engineer Intern
Ciena
Ottawa, CA
1mo
Develop automation infrastructure for next-generation ASIC devices used in optical communications.
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Field Application Engineer
Analogdevices
China, Shenzhen, Guangdong, Nanshan
1mo
Support customer implementations of ADI analog/digital/AI solutions through technical training, debugging, and system-level reviews.
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Intern- Silicon Design Validation Engineer
Micron
MSB, Singapore
1mo
Intern role focused on silicon design validation for advanced NAND products, developing validation plans, performing simulations, and analyzing measurement data.
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Intern- Silicon Design Validation Engineer
Micron
Singapore, Singapore
1mo
Intern role focused on silicon design validation for advanced NAND products, involving simulation, lab measurements, and data analysis.
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Senior FPGA Engineer
Lamresearch
US-CA-Fremont (1003)
1mo
Designing and implementing FPGA solutions for embedded controllers in semiconductor plasma etchers, bridging hardware and software to control peripheral devices and signal processing.
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Senior Advanced Development Discrete (ADA) Software Engineer
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Qualcomm
Singapore, Singapore
1mo
Design, develop, and implement software solutions for R&D EDA software systems supporting RF front-end module design and test.
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Systems Engineer, Platform Architecture
Apple
Austin, United States of America
1mo
Design and develop hardware/software interface technologies for chip development and verification, supporting next-generation silicon engineering teams.
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Front-end Design/Verification Engineer【1 year contractor】
MediaTek
HsinChu
1mo
Act as a window for glitch flow and methodology with DV EDA tools (including AI EDA), assisting users in reporting issues to tool vendors and resolving tool usage problems.
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Semiconductor Packaging Modeling and Simulation Engineer
ON Semiconductor
Waterloo, ON, Canada
$77k
1mo
Perform thermal-mechanical simulation for microelectronic packaging, assembly processes (Ag/Cu sintering), and system reliability analysis to support new power module development.
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Silicon Engineering INTERN
Microsoft
India, Karnataka, Bangalore
1mo
Designs, develops, modifies, and evaluates electronic parts, components, or integrated circuitry for digital electronic devices and systems; performs pre-silicon verification testing and analysis.
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Intern – DRAM Technology Physical Design and Block-Level PPA Optimization
Micron
Boise, Idaho, United States of America
1mo
Intern role optimizing power, performance, and area (PPA) for advanced memory products at the standard cell and logic block level.
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Internship - PDK Engineer
Infineon
Lexington, KY
1mo
Develop and improve parameterized cells (Pcells) for semiconductor devices and author DRC/LVS/RCX rule decks for PDK inclusion.
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Mechanical/Thermal Principal Design Engineer
Micron
Boise, ID - Main Site
1mo
Lead mechanical and thermal architecture for next-generation memory and AI computing platforms, driving design from concept through mass production.
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CAD Engineer - Signoff Infrastructure
Apple
Austin, United States of America
1mo
Develop full-stack web applications, dashboards, and data visualization tools for the Signoff infrastructure, the final verification stage in chip design.
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Engineer, IT
Micron
Fab 10W, Singapore
1mo
Manage the application lifecycle for software systems within a highly automated semiconductor manufacturing environment.
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Semiconductor Packaging Modeling and Simulation Engineer
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Onsemi
Waterloo, Ontario, Canada
$77k
1mo
Perform thermal-mechanical simulation for microelectronic packaging, assembly processes (Ag/Cu sintering), and system reliability analysis to support new power module development.
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Senior Engineer Thermo-mechanical Simulation (f/m/d)
Regensburg, BAYERN
1mo
Develop thermomechanical models and simulations to evaluate deformation and stress in microelectronic products, ensuring product reliability and minimizing failure risks.
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Production Analytical Solutions (PAS) Developer (m/f/d)
Advantest Europe GmbH
Böblingen, BADEN_WUERTTEMBERG
1mo
Translate product vision into scalable technical solutions and implement modular, production-grade tooling for high-volume manufacturing environments.
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GPU Architect - New College Graduate 2027
NVIDIA
China, Shanghai
1mo
Design and develop new hardware features, simulators, and testing infrastructure for future graphics and parallel processing architectures.
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AI Lead Architect - Silicon Design Execution
Altera
San Jose, California, United States
$206k
1mo
Lead the AI transformation of hardware design, verification, and implementation workflows at Altera, defining strategy and deploying AI/ML tools to accelerate chip development.
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PDK/CAD Design Automation Engineer
Qualcomm
Tijuana, Baja California, Mexico
1mo
Develop and support customized tools and flows for schematic & layout design, circuit simulation, IP characterization, and P&R automation within the Global Design Enablement team.
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Staff Engineer Simulation and Package Design Methodology (f/m/div)
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Infineon Technologies
Villach, Carinthia, Austria
1mo
Develop and support simulation methodologies, design flows, and tool environments for Chip-Package-Board (CPB) Co-Design and advanced package development in Linux-based HPC environments.
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Silicon Performance, Power and Binning Tools Engineer
NVIDIA
China, Shanghai
1mo
Build and optimize toolchains that translate silicon simulation data (power, noise, binning yields) into firmware tuning, product specs, and manufacturing limits using AI/LLMs.
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Staff Engineer Simulation and Package Design Methodology (f/m/div)
Infineon
Villach
1mo
Develop and support simulation methodologies, design flows, and tool environments for Chip-Package-Board (CPB) Co-Design and advanced package development in Linux-based HPC environments.
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Senior Software Development Engineer, Neural Graph Infrastructure
NVIDIA
US, CA, Santa Clara
$168k
1mo
Architecting and building next-generation software infrastructure for semiconductor design using graph neural networks to process trillion-edge scale graphs.
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Software Engineer II: Innovus R&D
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Cadence
Belo Horizonte, Minas Gerais, Brazil
1mo
Design and development of new algorithms and technology in automated clock-tree synthesis for the Innovus place and route tool.
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Senior Staff Engineer, Diagnostics and AI
Qualcomm
San Diego, California, United States of America
1mo
Define and evolve silicon Diagnostics and yield intelligence architectures, drive AI-enabled engineering transformation, and provide strategic technical leadership across Qualcomm's Yield Architecture and Engineering organization.
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Silicon Engineering Internship (6-month Program)
Microsoft
United States, California, Mountain View
1mo
Develops hardware solutions using performance instrumentation, logic design, verification, and circuit design to prevent bugs before production.
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Senior Engineer- memory compiler flow development
Arm
Bengaluru, India
1mo
Develop, improve, and support tools/flows for memory compiler development, focusing on generating physical views (GDSII, LEF, NDM, CDL) for embedded memories.
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Connectivity Systems Engineer, Staff
Qualcomm
Toronto, Ontario, Canada
$121k–$171k
1mo
Define and develop technologies for next-generation electrical and optical connectivity solutions, including system-level simulations and component specifications for AI and infrastructure computing.
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Sr. Principal Software Engineer, Physical Verification
Cadence
SAN JOSE
$161k–$299k
1mo
Design, develop, and implement robust software for physical verification of advanced semiconductor devices at leading-edge nodes.
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Principal CPU Power Modeling Engineer (San Diego, CA)
Qualcomm
San Diego, California, United States of America
$217k–$325k
1mo
Define and drive CPU power modeling strategy, methodology, and execution across Mobile, Compute, and XR/VR product segments to influence architecture and product-level power optimization.
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Software Engineer, Senior
Qualcomm
Toronto, Ontario, Canada
$101k–$151k
1mo
Design, develop, and validate embedded and cloud edge software, applications, and specialized utility programs to accelerate firmware development, chip characterization, test execution, SDK delivery, and GUI development for semiconductor products.
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EDA/CAD SW Engineer (Multiple Levels)
Qualcomm
San Diego, California, United States of America
$146k–$218k
1mo
Developing critical emulation CAD tools and algorithms for Qualcomm SoC needs, including synthesis, partitioning, place and route, and clock optimization.
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Lead Software Engineer
Cadence
Burlington, MA
$102k
1mo
Developing the world's fastest emulator compiler for Cadence's Palladium Platform, focusing on large-scale compile problems like logic optimization, distributed databases, and precompiler technologies.
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Founding Engineer
Clera
USA
$120k
1mo
Build and ship AI-assisted PCB design tools and EDA automation features, integrating manufacturing pipelines to own the end-to-end hardware-to-production workflow.
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Stage Ingénieur : Développement d’un outil d’analyse de performance pour simulations hardware (H/F)
Nxp
Caen
1mo
Develop an internal tool to extract and measure performance indicators from hardware simulations of digital components.
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Lead Product Engineer
Cadence
BANGALORE
1mo
Lead Product Engineer responsible for Synthesis flows including Logic Equivalence Checking (LEC) and Clock Latency Planning (CLP) to address design issues.
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Computer Science Senior Engineer for CAD - Cork, Ireland
Qualcomm
Cork, Ireland
1mo
Develop CAD tools, flows, and methodologies for VLSI design at advanced technology nodes (3nm and below) using automated reasoning and optimization.
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Project Director Design Flow (f/m/div)
Infineon
Munich
1mo
Lead complex international programs for design-flow software, infrastructure, and methodology, ensuring end-to-end accountability for scope, budget, risk, quality, and business outcomes.
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Computer/Data Science Staff Engineer for CAD - Cork, Ireland
Qualcomm
Cork, Ireland
1mo
Lead the development of CAD technologies, design methodologies, and automation solutions for next-generation VLSI design (3nm and below) using advanced optimization and AI techniques.
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Stage ingénieur : Analyse de la consommation et optimisation des tests pour les System-on-Chip (SoC) de nouvelle génération (H/F)
Nxp
Sophia-Antipolis (Valbonne)
1mo
Analyzing power consumption and optimizing test quality for next-generation System-on-Chip (SoC) designs using AI and automation.
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Field Applications Engineer (FAE)
Altera
Remote
$135k
1mo
Drive FPGA adoption and provide technical support to customer engineering teams for Altera programmable logic solutions.
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Stage Ingénieur : Application de l'Intelligence Artificielle à l'intégration de blocs RTL (ASIC/FPGA) (H/F)
Nxp
Sophia-Antipolis (Valbonne)
1mo
Develop an AI-based solution to automate and improve the reliability of RTL IP integration within ASIC and FPGA projects.
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EDA & PLM Systems Engineer
Micron
Boise, Idaho, United States of America
1mo
Technical lead for Siemens Xpedition and Teamcenter platforms supporting build operations in semiconductor hardware development.
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Stage ingénieur : Développement d’outils d’Intelligence Artificielle pour l’automatisation et la capitalisation des connaissances EMC/ESD (H/F)
Nxp
Toulouse
1mo
Develop AI workflows and intelligent assistants to automate engineering activities and structure historical technical knowledge for EMC/ESD robustness in integrated circuit design.
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