Senior/Staff NAND Design Rule Engineer
Core
Define physical design rules for next-generation 3D NAND development from conception to production ramp, ensuring accuracy and feasibility across layout and architecture options.
Role type
Senior/Staff IC NAND Design Rule Engineer
Builds
Next-generation 3D NAND memory products and storage solutions
Domain
Semiconductor manufacturing / Memory technology / Process Integration
Required skills
Semiconductor device physics, VLSI silicon processing, Python programming, CAD tools (Cadence Virtuoso, K2view, Mentor Graphics DRV/RVE), Design rule checking (DRC), Mask data generation algorithms, Non-volatile memory technology knowledge
Preferred skills
Experience with yield enhancement, test structure development, unit process development, agentic capabilities development
Technologies
Python, Cadence Virtuoso, K2view, Mentor Graphics DRV/RVE, DRC tools, Database-to-reticle data transfer
Responsibilities
Define physical design rules for NVM technologies, interact with process integration teams to maintain technology updates, evaluate layout/architecture feasibility with design teams, develop automated solutions for design rule coverage, support DRC of base and mask layers, define algorithms for mask data generation
Seniority
Senior/Staff, hands-on IC
