Senior/ Staff Design Automation Engineer, Scribe Layout Design Non-Array
Core
Design, layout, and verification of CMOS electrical test structures for device development, compact modeling, reliability modeling, and fab process monitoring.
Role type
Senior IC design automation engineer (CMOS test structures)
Builds
Physical layouts, floor plans, and verified test structures for CMOS modules
Domain
Semiconductor manufacturing / CMOS process technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
EDA tools and CAD flows, Generative AI and LLM-based automation, SKILL/SKILL++, Python, Linux, CMOS process manufacturing knowledge, layout design rules
Preferred skills
Patent disclosure experience, research paper publication, mentoring junior engineers
Technologies
SKILL, SKILL++, Python, Perl, Tcl, Linux
Responsibilities
Develop programmatically defined P-cell devices for CMOS modules, implement scalable layout automation methodologies, generate DUTs using PCELLs, perform floorplan and placement of devices, wire DUTs to pads, evaluate and implement new tools to improve automation flows
Seniority
Senior, hands-on IC