STAGE – Génération de netlists SPICE multi-simulateur – F/H
Core
Develop a simulator-independent abstraction layer for SPICE netlist generation and measurement extraction to improve IP validation flow portability and reusability.
Role type
Intern, IC design automation engineer (SPICE)
Builds
Simulator-agnostic netlist generation and measurement extraction tools
Domain
Semiconductor, IC design automation, SPICE simulation
Required skills
SPICE simulation environments, netlist writing, simulation launch, measurement extraction, programming, tool automation
Preferred skills
Tcl, shell/bash/csh, Python, compilers, parsers, code generation (Jinja), pytest
Technologies
SPICE, Tcl, Python, Jinja, pytest
Responsibilities
Analyze existing IP validation flow and identify simulator-specific dependencies, Design simulator-independent architecture for netlist generation and measurement extraction, Implement and validate the proposed solution, Document the solution, limitations, and best practices
