Design Verification Infrastructure & Performance Engineer
Core
Optimize simulation and build flows for AMD silicon development by improving runtime, memory usage, and verification productivity.
Role type
Senior IC silicon design infrastructure engineer
Builds
Scalable simulation and build workflows for next-gen processors
Domain
Semiconductor / Silicon Design / Verification Infrastructure
Required skills
Scripting (Python, Perl, Shell, Ruby), Unix/Linux systems, HDL environments (Verilog/SystemVerilog/UVM), Performance analysis, Automation development, Git/Perforce, Object-oriented programming
Preferred skills
SQL/database administration, LSF knowledge, Simulation/build system optimization
Responsibilities
Drive enhancements in simulation and build methodologies, Analyze simulation performance and identify runtime/memory bottlenecks, Develop automation and tools to detect inefficient coding practices, Improve simulation speed in constrained-random and coverage-driven verification environments, Coordinate with infrastructure engineers to adopt industry-standard workflows, Support continuous process and tool improvements across the silicon design ecosystem
