Staff Physical Design Verification, CAD
Core
Develop, integrate, and debug Electronic Design Automation (EDA) tools and flows for the physical layout and design of CMOS integrated circuits to increase design productivity and reliability.
Role type
Staff IC Physical Design Verification & CAD Engineer
Builds
Production-ready EDA tool flows, verification infrastructure, and next-generation CAD software for memory design.
Domain
Semiconductor / Memory / Physical Design / EDA
Deliverable
production ML models | product features | infrastructure
Required skills
Unix and shell scripting, CMOS circuit knowledge, deep-submicron physical design, layout design rules, EDA tool integration, tool evaluation and deficiency identification, engineering infrastructure development
Preferred skills
Calibre DRC/LVS, floorplanning, automated P&R, SPF extraction, Verilog/Verilog-A, VCS, Spice/FastSpice, FineSim/PrimeSim, HSPICE, RTL-to-GDS flows, Cadence Virtuoso DFII, SKILL programming, Python, Python Qt frameworks
Technologies
Calibre, Virtuoso, SKILL, VCS, HSPICE, Python, Qt
Responsibilities
Develop tools and methodologies to increase design productivity; Integrate commercial EDA tools into design flows; Provide training and support to end users; Undertake R&D of next-generation CAD software; Evaluate EDA industry trends and internal tool deficiencies; Define flows for efficiency and cost improvement; Maintain engineering infrastructure
Seniority
Staff, hands-on IC with strategic influence
