Engineer- Tech PNR methodology
Core
Develop and deploy design methodologies, flows, scripts, and automation for advanced semiconductor process nodes to achieve optimal performance, power, and area (PPA) on CPU designs.
Role type
Senior IC EDA technology enablement engineer (via careerplan.io/jobs/101024454672-engineer-tech-pnr-methodology-at-arm)
Builds
EDA tool flows, design methodologies, and automation scripts for advanced node processes
Domain
Semiconductor manufacturing / VLSI design / EDA tools
Required skills
Floorplan, PDN, Timing, Power, and Physical design expertise; EDA tool-flows and PPA analysis; VLSI CAD Software and automation architecture; Python, C, Tcl programming; Git and distributed processing
Preferred skills
Multi-die SoC design flows; Data analytics and metrics
Technologies
Python, C, Tcl, Git, EDA vendor tools
Responsibilities
Drive EDA technology enablement from early development through production readiness; Develop and deploy design methodologies, flows, scripts, and automation; Develop strategy and roll-out for EDA tools roadmap and features; Analyze requirements and define CAD solutions including external EDA tools integration; Collaborate with EDA vendors to debug tool issues and influence improvements; Lead product implementation with internal design teams, foundry, and partners
Seniority
Senior, hands-on IC