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Software Engineering
› Hardware Verification
Hardware Verification
799 open positions
Front End Central Product Integration Engineer – Test & Product Yield Integration (Senior / Staff / Principal)
Micron
Taichung City, Taichung City, Taiwan
2mo
Lead global Product Integration initiatives to improve yield, quality, and benchmark performance across technology nodes and products by centralizing project information and driving end-to-end test flow strategies.
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High Speed PHY FW Engineer
Cadence
SAN JOSE
$102k–$189k
2mo
Developing physical IP firmware for industry-standard high-speed serial-link protocols (SERDES) to enable adaptation, equalization, and control algorithms in system-on-chip designs.
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New College Grad - Computer Engineer, Engineering Automation
Micron
Richardson, TX
2mo
Develop, enhance, and debug CAD tools and flows to improve the efficiency and quality of NAND, DRAM, and HBM memory designs.
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AI/ML Software Engineer
Siemens-Eda
New Cairo, EGY, Egypt
$24k–$24k
2mo
Design, develop, test, and deploy web applications and services leveraging AI/ML technologies for chip, board, and system design.
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Technical Program Manager, Product Software
Tenstorrent
Santa Clara
$100k–$100k
2mo
Leading end-to-end software development for next-generation Chiplet based SiP across AI, CPU, Memory, and I/O domains from architecture to tape-out.
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Power Architect
Tenstorrent
Toronto
2mo
Architecting and optimizing power efficiency for high-performance AI compute systems and RISC-V CPUs.
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High Level Synthesis Compiler Engineer
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Altera
Toronto, Ontario, Canada
2mo
Required skills: C++, digital design, FPGA background, compiler development, mentorship Preferred skills: PhD, simulation, formal, debug environments, high-level design flows (HLS) Technologies: LLVM, MLIR, FPGA, ASIC, EDA Responsibilities: Develop and…
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Distributed Systems Engineer
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Cadence
Port Moody, British Columbia, Canada
$90k–$166k
2mo
Building scalable data processing infrastructure and orchestration for a next-generation distributed transistor-level electromigration and IR drop analysis tool.
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Principal Sourcing Engineer, Semiconductor Backend
Microsoft
United States, Washington, Redmond
2mo
Develop long-term sourcing strategies and execute them for OSAT, Substrate, and Test suppliers to deliver custom silicon solutions for Azure Hardware Systems & Infrastructure teams.
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MTS - Design Enablement (PDK, Pcell developer)
GlobalFoundries
Singapore
2mo
Developing design components, tech files, runtime code, and automation tools for Process Design Kits (PDKs) to enable electronic design automation.
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Photo MDE Principal Lead Engineer
Micron
Boise, ID - Main Site
2mo
Leading photolithography process development and team operations to advance next-generation DRAM technology.
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Product Engineer(DVT)
Siemens-Eda
Seongnam-Si, KOR, South Korea
2mo
Define product features and methodologies for Siemens Functional Verification tools to address verification challenges in chip, board, and system design.
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Principal Systems Performance Engineer – Modeling
Micron
Longmont-MAX- Office, CO
2mo
Design and evolve data center-scale logical models to evaluate future SSD product scenarios and simulate tradeoffs across large-scale cloud environments.
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Sr. Node Development Product Engineer - DRAM Technology
Micron
Boise, ID - Main Site
2mo
Drive new process node startup, qualification, yield, and ramp to world-class performance for industry-leading DRAM technology.
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Software Engineer II - Clock Tree Synthesis (CTS), Innovus R&D
Cadence
CAMBRIDGE
2mo
Develop and optimize high-performance EDA algorithms for Clock Tree Synthesis (CTS) to improve chip performance and power efficiency.
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Front End CPIE Process Integration (PI) Member of Technical Staff(MTS)
Micron
Fab 10A, Singapore
2mo
Drive best-in-class product maturity (yield, repair density, DPM) and process integration across DRAM/NAND manufacturing sites to achieve product maturity at the fastest speed.
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Package Health Yield (Senior/Staff/Principal) Engineer, APTD
Micron
Fab 10A, Singapore
2mo
Develop advanced packaging technology strategies for high-performance memory products, focusing on test architecture, coverage, and yield optimization to ensure robust packaging solutions.
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Principal Engineer
Siemens-Eda
Calgary, AB, Canada
2mo
Architecting and implementing advanced algorithms and software designs for industry-leading electronic design automation (EDA) simulation tools.
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Sr. RF Front-End Module Design Engineer (RFIC Engineering)
SpaceX
Irvine, CA
$160k–$160k
2mo
Design, simulate, and optimize compact multi-chip modules (MCMs) containing custom RF front-end components for 5G NR, LTE, and Wi-Fi applications.
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Entry Level: Radio Algorithm Developer
Ericsson AB
Lund, Sweden
2mo
Designing advanced digital signal processing algorithms and efficient hardware implementations for current and next-generation radio solutions.
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Staff/Principal Logical Design Engineer
Graphcore
Bristol
2mo
Designing micro-architecture specifications and RTL for AI compute chips.
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CAD Engineer
Broadcom
Singapore-Yishun
2mo
Providing best-in-class development and support for CAD tool flows focused on advanced process nodes.
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Lead Diagnostics Software Engineer, ATE Integration
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AMD
Markham, Ontario, Canada
2mo
Lead Diagnostics Engineer migrating post-silicon software validation and System-Level Tests (SLT) into Automated Test Equipment (ATE) and Wafer Sort environments for data center GPU IPs.
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Lead Member of Technical Staff
Siemens-Eda
Noida, IND, India
2mo
Develop and deliver new features for formal verification software, ensuring quality, scalability, and testability across the product portfolio.
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Senior Software Developer – Algorithms and AI for Chip Design Automation - Santa Clara*
Siemens-Eda
Santa Clara, CA, United States
2mo
Developing AI-driven software for analog and custom IC design automation, solving complex placement, routing, and optimization problems for chips powering AI, cloud, and automotive systems.
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Theorem Proving Engineer
Arm
Austin, Texas
$198k–$198k
2mo
Analyze data path RTL designs and algorithms, develop abstract C models, establish equivalence with commercial checkers, and formally verify correctness against high-level architectural specifications using the ACL2 theorem prover.
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Platform Technologies Language & Frontend Design Engineer
Sifive
Santa Clara, California, United States
$140k–$140k
2mo
Architecting, building, and maintaining cutting-edge tools for System-on-Chip (SoC) design, specifically applying programming language expertise to design domain-specific languages for hardware design.
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Principal Engineer, High-Speed IO & Memory Systems
Sambanovasystems
Austin, TX
2mo
Post-silicon validation and bring-up of high-speed IO and memory subsystems for AI compute platforms, ensuring stability and performance from first silicon through customer deployment.
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Director, Software Engineering
Asm
AZ Phoenix (ASM America Inc.)
2mo
Lead global software engineering strategy and execution for semiconductor equipment software, driving innovation and scalable solutions for customers.
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Staff Embedded SW/FW Engineer (Bringup) - Bengaluru
Graphcore
Bengaluru
2mo
Developing C code to validate cutting-edge, high-performance AI chips and platforms, specifically focusing on post-silicon bringup and first silicon validation.
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DFT Engineer
Graphcore
Remote
2mo
Designing and implementing Design for Testability (DFT) architectures and flows for next-generation AI silicon chips targeted at data center applications.
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Silicon Verification Engineer
Graphcore
Bristol
2mo
Own verification that turns complex silicon architecture into reliable AI compute hardware.
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Principal Product Engineer
Graphcore
Bristol
2mo
Ensuring Graphcore AI chips and systems are manufactured with optimized yield, quality, and cost throughout the product lifecycle.
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Principal Embedded SW/FW Engineer (Bringup) - Bengaluru, multiple vacancies
Graphcore
Bengaluru
2mo
Validating cutting-edge, high-performance AI chips and platforms by bringing first silicon to life and functionally validating it.
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Software Engineer - Principal
Siemens-Eda
Bangalore, IND, India
2mo
Developing core algorithmic advances and software design/architecture for the QuestaSim R&D team to build new engines and support existent code for electronic design automation tools.
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CAD Engineer
NVIDIA
US, CA, Santa Clara
$116k–$116k
2mo
Install, configure, and support foundry techfiles; debug design, tool, and techfile errors for IC designers; develop automation flows and scripts to improve productivity in custom circuit design.
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SMTS, Design Rule Enablement Team TPG
Micron
Hiroshima, Japan
2mo
Lead Design Enablement efforts for DRAM technologies by coordinating cross-functional engineering teams to develop and optimize design rules, requirements, and test structures from early development through manufacturing.
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Senior Python Software Developer
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Pdf Solutions
Vancouver, British Columbia, Canada
$120k–$120k
2mo
Building robust Machine Learning modeling pipelines in Python to optimize semiconductor manufacturing metrics like yield and tolerance.
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Software Engineer (C++/DS/Algo)
Siemens-Eda
Kolkata, IND, India
2mo
Design and implement front-end compiler components for Electronic Design Automation (EDA) tools, processing Hardware Description Languages (Verilog, SystemVerilog, VHDL) to enable chip, board, and system design.
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Senior Engineer, Advanced Process Modeling
Micron
Hyderabad - Phoenix Aquila, India
2mo
Develop and validate process/structure models using machine learning and statistical techniques to build predictive analytics and decision automation systems for memory development and manufacturing.
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Software Developer: C++ / Linux / ILT
Siemens-Eda
Wilsonville, OR, United States
$90k–$162k
2mo
Design, implement, and enhance the platform for Calibre Resolution Enhancement Technology (RET) and Inverse Lithography (ILT) tools running on highly scalable distributed platforms.
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IC RTL2GDS Architect, AE
Cadence
SAN JOSE
$158k–$158k
2mo
Technical leader driving strategic customer engagements and next-generation EDA & Agentic-AI solutions for leading semiconductor companies.
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Architecture Validation Engineer
Arm
Bengaluru, India
2mo
Develops new architecture models and design performance studies to evaluate key architecture features for ARM's future roadmap, while validating CPU behavior and architecture compliance using embedded software-style test development.
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Front-End Fab Category Manager
Analogdevices
US, OR, Beaverton
$96k–$96k
2mo
Develop and execute sourcing strategies for fab equipment and services to support ADI's manufacturing performance in Oregon, Washington, Massachusetts, and Ireland.
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Technology Enablement Principal - DFT, In-System Test
Siemens-Eda
Edinburgh, GBR, United Kingdom
$82k–$82k
2mo
Driving adoption of Tessent In-System Test solutions by supporting architecture and methodology definition for customers at the early product definition phase.
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Analog/Mixed Signal Verilog Modeling Design Engineer
Broadcom
USA-CA Irvine Alton Parkway Bldg 1
2mo
Develop Digital-Mixed Signal (DMS) models of analog IPs (touch controller AFEs, wireless power charging, health sensing AFE, satellite AFEs) using SystemVerilog for chip verification.
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Senior C++ Software Engineer - Chip Design Tools
NVIDIA
US, CA, Santa Clara
$152k–$242k
2mo
Develop and support high-performance infrastructure tools for chip design engineers to automate build and verification of architectural, RTL, and gate-level designs.
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Senior / Principal Engineer, Software Engineering
Asm
Singapore (ASM Front-End Mfg (S) Ltd)
2mo
Designing and leading software for advanced semiconductor packaging and hybrid bonding equipment, integrating robotics, motion control, and thermal systems.
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Software Engineering Intern (Spring 2027)
Asm
AZ Phoenix (ASM America Inc.)
2mo
Deliver end-to-end automation and tooling for CSA configuration, validation, licensing, and log visibility to support engineering and QA teams.
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Software Systems Engineer II - Quality Focus
Asm
AZ Phoenix (ASM America Inc.)
2mo
Design and execute system-level validation strategies for software controlling semiconductor manufacturing equipment, focusing on reliability, robustness, and release readiness.
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