Staff Physical Design Verification, CAD
Core
Develop, integrate, and debug Electronic Design Automation (EDA) tools and flows for the physical layout and design of CMOS integrated circuits to increase design productivity and reliability.
Role type
Staff IC Physical Design CAD Engineer
Builds
Next-generation CAD software, integrated EDA tool flows, and engineering infrastructure for memory design teams.
Domain
Semiconductor / Memory / Physical Design / EDA
Required skills
Unix and shell scripting, CMOS circuits, deep-submicron physical design, layout design rules, EDA tool integration, tool evaluation and deficiency identification, engineering infrastructure development.
Preferred skills
Calibre DRC/LVS, floorplanning, automated P&R, SPF extraction, Verilog/Verilog-A/ncverilog, VCS, Spice/FastSpice, FineSim/PrimeSim, HSPICE, RTL-to-GDS flows, Agentic AI, Cadence Virtuoso DFII, SKILL programming, Python, Python Qt frameworks.
Technologies
Calibre, Virtuoso, SKILL, VCS, HSPICE, Python, Qt, Unix
Responsibilities
Develop tools, flows, and methodologies to increase productivity and reliability of memory designs; Integrate commercial EDA tools into design flows; Provide training, documentation, and support to end users; Undertake independent R&D of next-generation CAD software; Identify deficiencies of current tools and flows; Evaluate tools with internal customers to define improvement flows; Develop, maintain, and support engineering infrastructure.
Seniority
Staff, hands-on IC with strategic influence
