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Software Engineering
› Hardware Verification
Hardware Verification
1,144 open positions
CAD Software Developer Engineer
Apple
Israel, Israel
1mo
Architecting scalable, distributed solutions and LLM infrastructure to optimize chip design workflows and enable faster development for CAD design teams.
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CST Application Engineer
Cadence
SAN JOSE 09, US
$74k
1mo
Entry-level rotational program for STEM graduates providing front-line design services, technical sales, and customer support for advanced EDA tools to silicon design and design automation customers.
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CST Application Engineer - Physical Systems
Cadence
LIVONIA 01, US
$78k
1mo
Entry-level Application Engineer supporting customers with physical system simulation and analysis using CAE tools.
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CST Application Engineer Intern - Physical Systems
Cadence
SAN JOSE, US
1mo
Summer 2027 internship for engineering students to gain hands-on training in applications supporting engineering analysis, system design, and tools using Cadence CAE tools.
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R&D Engineer, Staff Engineer
↗
Synopsys
KA, IN
1mo
Validating and developing semiconductor library views and power models (SPIPROF, CDEV, PWCDEV) to ensure production-ready IP for chip tape-outs.
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Principal Algorithms Engineer (physics)
ASML
San Jose, CA, USA
$227k–$312k
1mo
Lead the development of advanced physics-based modeling and simulation technologies for e-beam semiconductor inspection systems, including SEM image formation and electron-beam interactions.
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Internship – Analog-Mixed Signal Architect Support for Automotive Microcontroll (f/m/div)
Infineon
Villach
1mo
Support automotive microcontroller development by analyzing analog mixed-signal circuits, investigating power consumption, and applying AI/ML-driven solutions to EDA workflows.
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Sr. Principal IC Digital Flow AE
Cadence
SAN JOSE, US
$148k–$276k
1mo
Senior Application Engineer providing technical support and guidance for Cadence's digital implementation and signoff tools (Synthesis, P&R, Signoff) to help customers achieve PPA targets and design closure.
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Cores Verification Lead
Advanced Micro Devices, Inc
ONTARIO-HOME OFFICE, Canada
1mo
Lead the design, development, and optimization of scalable build infrastructure to reduce model build turnaround times and improve engineering productivity for next-generation microprocessor designs.
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Sr. FPGA Engineer - Vivado
Advanced Micro Devices, Inc
Belfast, United Kingdom
1mo
Technical Marketing Engineer driving the Vivado and next-generation tool product roadmap, focusing on design flows, Tcl/scripting infrastructure, and IP services to serve customer needs and enable FPGA/Adaptive SoC design processes.
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PDK Enablement Engineer
Micron
Folsom, California, United States of America
$190k
1mo
Collaborate with CAD teams, tool vendors, and foundries to ensure PDK compatibility and performance, while developing documentation and conducting training for design teams.
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Principal Product Engineer
Cadence
HSINCHU, TW
1mo
Drive development and customer engagement for Virtuoso with latest Layout Automation and AI-driven flows.
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Staff Software Application Engineer
SiFive
Santa Clara, California, United States
$159k
1mo
Staff Software Applications Engineer supporting customers in designing with SiFive RISC-V IP, resolving software issues, and maintaining datacenter hardware development platforms.
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Senior VLSI Methodology Engineer
NVIDIA
US, CA, Santa Clara
$136k
1mo
Design automation infrastructure for library modeling, quality checks, and release flows for NVIDIA's GPU and SOC silicon designs.
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PDK Enablement Engineer
Micron
Folsom, CA, US
$190k
1mo
Enable PDK compatibility and performance by collaborating with CAD teams, tool vendors, and foundries; develop documentation, troubleshoot issues, and conduct training for design teams.
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Senior Physical Design AI Engineer
NVIDIA
India, Bengaluru
1mo
Build agentic AI solutions to improve productivity, efficiency, and quality in Physical Design Implementation teams.
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CAD Engineer
Broadcom
Singapore-Yishun
1mo
Develop, maintain, and support CAD tool flows and utilities for advanced process nodes, providing hands-on support for design/layout issues.
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AI Architect, Agentic AI for Chip Design & EDA
Altera
San Jose, California, United States
$210k
1mo
Lead the development of Agentic AI, Generative AI, and machine learning technologies to transform the end-to-end silicon development lifecycle, from architecture and RTL development through physical design, manufacturing, and yield optimization.
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Software Engineer - C++ / Compiler
Siemens-Eda
Burlington, MA, United States
$90k–$162k
1mo
Develop and improve the compiler software that analyzes customer circuit designs to map them onto emulation hardware resources for functional verification.
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Gate-level IR/EM CAD/NLP Engineer
Apple
Austin, United States of America
1mo
Develop ML and LLM applications to analyze IR/EM issues in silicon design, generate reports, and automate signoff flows for Apple processors.
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Senior Digital CAD Engineer
ON Semiconductor
Brno, South Moravia, Czech Republic
1mo
Evaluate, acquire, develop, integrate, and support digital design tools and methodologies for global development teams.
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STA - CAD Engineer
Advanced Micro Devices, Inc
Austin, Texas
1mo
Develop and deploy timing analysis (STA) methodologies and flows for next-generation AMD processor designs across embedded, server, desktop, and laptop segments.
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Summer 2027 Hardware Engineer Intern
Advanced Micro Devices, Inc
Cambridge, United Kingdom
1mo
Hardware Engineering intern responsible for discrete and embedded hardware products and building applications to improve hardware organization efficiency.
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Gate-level IR/EM CAD/NLP Engineer
↗
Apple
Austin, TX, US
$185k
1mo
Developing an analytic platform to identify and recommend solutions for signoff IR/EM analysis using machine learning and large language models.
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Staff CAD Engineer
Micron
Richardson, Texas, United States of America
1mo
Lead complex CAD and EDA tool development, enhancement, and support projects for semiconductor design flows, integrating AI and machine learning to improve engineering productivity and design quality.
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STAGE - Création d’un agent IA pour les flots de conception numérique et analogique - F/H
STMicroelectronics
Crolles, France
1mo
Build an AI agent to assist with digital and analog chip design workflows using technical documentation and system support data.
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Early Career Analog Mixed-Signal Modeling Software Engineer (m/f/d)
Apple
Munich, Germany
1mo
Develop specialized software tools and simulation platforms to design analog mixed-signal circuits for Apple's custom silicon chips.
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CST Application Engineer Intern - Silicon
Cadence
SAN JOSE, US
1mo
Summer 2027 internship supporting system and package design, digital/analog IC design, physical design, verification, and AI applications for silicon and systems.
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Engineer Ecosystem Enablement
GlobalFoundries
SGP - Woodlands, SG
1mo
Qualify and validate semiconductor IP libraries across technology platforms, ensuring compatibility with PDK updates and supporting customer tape-outs.
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Stage ingénieur : Génération et qualification de modèles comportementaux pilotées par l’IA (F/H)
Nxp
Toulouse, FR
1mo
Develop innovative methodologies and Python-based AI agents to improve the generation and qualification of surrogate behavioral models for semiconductor design.
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Principal Engineer, Memory CAD Engineering
Micron
Richardson, Texas, United States of America
1mo
Lead the development, evaluation, and enhancement of CAD and EDA tools, flows, and methodologies for next-generation memory and storage products.
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Gate-level IR/EM CAD/NLP Engineer
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Apple
Sunnyvale, CA, US
$150k–$278k
1mo
Developing ML and LLM applications to understand, explain, and interact with EDA software for IR/EM analysis and signoff.
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PCB Layout Automation Intern
Hpe
Sunnyvale, California, United States of America
$73k–$85k
1mo
Develop automation tools and utilities for high-speed PCB layout projects using Cadence Allegro and SKILL scripting.
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Principal Engineering Platform AI Architect
Arm
Cambridge, United Kingdom
1mo
Define target architecture and roadmaps for AI-enabled engineering platforms, toolchains, and workflows across silicon design, software development, and CI/CD.
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Sr. Fellow - Software Architect - EDA Software Development
Advanced Micro Devices, Inc
San Jose, California
1mo
Lead the evolution of software architecture and next-generation products for the Vivado EDA software team.
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Sr. Technical Program Manager- CPU Cores
Advanced Micro Devices, Inc
Fishkill, New York
1mo
Drive adoption of AI-driven methodologies and tooling across x86 CPU core development (verification, RTL design, physical design) to improve engineering efficiency and design quality.
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Director -AI Driven Silicon Design
Advanced Micro Devices, Inc
Fishkill, New York
1mo
Lead organization-wide adoption of AI-driven methodologies across x86 core development workflows, including functional verification, RTL design, and physical design.
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CAD/Emulation Engineer
Ceva
Ra'anana, Israel
1mo
Develop and maintain automation scripts for front-end Emulation and VLSI CAD flows and infrastructure.
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VP of Worldwide Field Engineering
proteanTecs
Santa Clara, United States
1mo
Lead global Field Engineering organization and own the technical customer journey for on-chip monitoring solutions in semiconductors.
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CAD Engineer (Digital)
Analogdevices
India, Bangalore, Nova
1mo
Develop and drive Design-for-Test methodologies and automate digital flows for corporate-wide semiconductor design using EDA tools.
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Software Engineer – DFT CAD Tools (RDSS Intern)
NVIDIA
Taiwan, Taipei
1mo
Design and develop in-house CAD software for Design for Test (DFT) to validate and ship large chip designs efficiently.
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Software Engineer – DFT CAD Tools (RDSS Intern)
NVIDIA
Taiwan, Taipei
1mo
Design and develop in-house CAD software for Design for Test (DFT) to validate and ship large chip designs efficiently.
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Tools and Methodology Engineer, CAD DFT (RDSS Intern)
NVIDIA
Taiwan, Taipei
1mo
Develop and optimize CAD tools and Design for Test (DFT) strategies to support semiconductor manufacturing and testing processes.
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Intern - Next Gen HBM Platform Arch
Micron
Folsom, California, United States of America
1mo
Develop future High Bandwidth Memory (HBM) platforms by evaluating electrical, thermal, and power delivery architectures for advanced memory systems.
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MBIST Diagnostics Engineer - Sr Staff/Staff Engineer
Qualcomm
Hsinchu City, Taiwan
1mo
Lead the development of advanced memory diagnostic methodologies and tools for next-generation SoCs, focusing on DRAM testing, failure analysis, and AI/ML-based pattern recognition to improve memory yield and reliability.
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Staff ENGINEER, HIG HBM-ARCHITECTURE
Micron
Bengaluru, Karnataka, India
1mo
Define and implement end-to-end DFT architectures for HBM base die and DRAM die to ensure quality, yield, and performance across complex multi-die architectures.
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Staff ENGINEER, HIG HBM-ARCHITECTURE
Micron
Bengaluru, India
1mo
Define and implement end-to-end DFT architectures for next-generation HBM base die and DRAM die to ensure quality, yield, and performance across complex multi-die architectures.
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IT Software Engineer
Micron
Boise, ID - Main Site, US
1mo
Develop, test, maintain, and support manufacturing and automation software for 300mm fabs globally.
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Intern - Engineer, HIG HBM DTPCO
Micron
Richardson, Texas, United States of America
1mo
Develop first-principles understanding of HBM cube limitations and validate hypotheses through silicon data and custom bench-level characterization under thermal, mechanical, and electrical stress.
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Tools and Methodology Engineer, CAD DFT (RDSS Intern)
NVIDIA
Taiwan, Taipei
1mo
Develop and optimize CAD tools and Design for Test (DFT) strategies to ensure flawless manufacturing and testing processes for semiconductor chips.
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