Stage Ingénieur : Génération semi-automatique de modèles, stimuli et testbenches par agents IA (F/H)
Core
Developing AI agents to semi-automatically migrate legacy integrated circuit behavioral models to newer technology nodes and generate associated verification stimuli and testbenches.
Role type
Research intern (IC verification & AI agents)
Builds
AI agents for model migration, code generation, and automated verification workflows
Domain
Semiconductor / Integrated Circuit Verification / Mixed-Signal Electronics
Deliverable
production ML models | product features
Required skills
Python programming, analog/digital electronics fundamentals, hardware description languages (Verilog/SystemVerilog/VHDL), verification methodologies, generative AI concepts
Preferred skills
Model adaptation strategies, automated testing frameworks, technical documentation
Technologies
Python, Verilog, SystemVerilog, VHDL, Verilog-AMS, AI agents
Responsibilities
Analyze legacy model structures and dependencies; Define semi-automated migration methodologies; Develop AI agents for model analysis and code generation; Generate representative stimuli and testbenches; Establish evaluation metrics for automation and code quality; Document solutions and industrialization paths
Seniority
Intern