Stage Ingénieur : Génération semi-automatique de modèles, stimuli et testbenches par agents IA (F/H)
Core
Developing AI agents to semi-automatically migrate legacy integrated circuit behavioral models to newer technology nodes and generate associated verification stimuli and testbenches.
Role type
Research intern (IC verification & AI agents)
Builds
AI agents for model migration, automated stimuli, and testbenches for pre-silicon verification
Domain
Semiconductor / Integrated Circuits / Mixed-Signal Verification
Deliverable
production ML models
Required skills
Python, Analog/Digital electronics basics, Hardware description languages (Verilog/SystemVerilog/VHDL), Verification methodologies, Generative AI, Code generation
Preferred skills
Mixed-signal simulation environments, Automated evaluation metrics
Technologies
Python, Verilog, SystemVerilog, VHDL, Verilog-AMS, Generative AI
Responsibilities
Analyze legacy model structures and dependencies; Define semi-automated migration methodologies; Develop AI agents for analysis and code generation; Generate representative stimuli; Develop testbenches for regression detection; Establish evaluation metrics; Document solutions and industrialization paths
