CareerPlan

Sr. Physical Design Engineer

Santa Clara, California, United States of AmericaFull-time$135k–$202k2026-11-09 → 2026-11-10

Core

Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power products.

Role type

Senior IC physical design engineer (ASIC/SoC)

Builds

ASIC blocks and System-on-Chip (SoC) IP

Domain

Semiconductor / Hardware Design

Required skills

ASIC design, digital/analog design, RTL to GDS flow, place and route, timing analysis, power analysis, verification methods, scripting, EDA tools

Preferred skills

Master's degree in Electrical/Computer Engineering, 3+ years ASIC experience, architecture design tools, scripting languages

Technologies

Virtuoso, RTL to GDS Flow

Responsibilities

Create architectures, circuit specifications, logic designs, and system simulations; Evaluate process flow from high-level design to synthesis, place and route, timing, and power; Write detailed technical documentation for EDA/IP/ASIC projects

Seniority

Senior, hands-on IC