ASIC Development Technical Leader
Core
Lead full-chip physical design and RTL-to-GDSII implementation for advanced process nodes (7nm/5nm/3nm) in Cisco's core switching, routing, and wireless products.
Role type
Senior IC ASIC Physical Design Technical Leader
Builds
High-performance silicon chips for global networking infrastructure
Domain
Semiconductor / ASIC Physical Design
Required skills
Full-chip floorplanning, RTL-to-GDSII flow, hierarchical implementation, static timing analysis, power integrity analysis, Python scripting, EDA tool expertise (Innovus, Tempus/Primetime, Calibre), low-power design (UPF)
Preferred skills
Custom clock mesh/H-tree design, physical design convergence, signoff methodology definition, AI tool integration for productivity
Technologies
Innovus, Tempus, Primetime, Redhawk, Voltus, Calibre, Pegasus, UPF, Python
Responsibilities
Create full-chip floorplans based on architecture and IP constraints; Perform hierarchical implementation including partitioning, pin assignment, and clock planning; Optimize RTL-to-GDSII flow for performance, power, and die size; Analyze and enhance EDA tool flows; Collaborate with system, package, and validation teams; Define and validate signoff methodologies with foundry and IP vendors.
Seniority
Senior, hands-on IC
