ASIC Design Technical Lead (CPU subsystems)
Core
Lead the architecture and design of complex CPU subsystems for next-generation high-performance networking switch ASICs, managing the full development lifecycle from specification to post-silicon bring-up.
Role type
Senior IC ASIC Design Technical Lead (CPU subsystems)
Builds
High-performance networking switch ASICs for Cisco's core Switching, Routing, and Wireless products
Domain
Semiconductor hardware design, networking infrastructure
Required skills
RISC-V/ARM/ARC microarchitecture, on-chip interconnect fabrics (AXI, CHI, NoC), PCIe subsystems, SystemVerilog RTL development, pre-silicon verification, CDC/RDC, synthesis/timing/constraints, post-silicon bring-up
Preferred skills
CPU/SoC subsystem architecture leadership, Boot/Security/Root of Trust (RoT), secure boot chains, debug/trace infrastructure (CoreSight, RISC-V Debug)
Technologies
SystemVerilog, RISC-V, ARM, ARC, AXI, CHI, NoC, PCIe, CoreSight
Responsibilities
Define driver interfaces, register maps, and memory consistency models; collaborate with SDK, BSP, and Network OS teams; support early emulation and FPGA platforms
Seniority
Senior, hands-on IC
