ASIC/FPGA Methodology Engineer
Core
Develop and maintain methodologies for ASIC/FPGA design, verification, and implementation, integrating workflows and tools to support RTL design development.
Role type
Senior IC ASIC/FPGA Methodology Engineer
Builds
ASIC/FPGA design flows, verification environments, and CI/CD pipelines
Domain
Semiconductor hardware design (ASIC/FPGA)
Required skills
FPGA development tools (Vivado, Quartus), ASIC design flows, SystemVerilog, UVM, timing analysis, synthesis, timing closure, CI/CD workflows, Linux utilities (Git, Docker, LSF, ClearCase), RTL design (Verilog)
Preferred skills
System-level integration and validation, debugging complex hardware/software issues, technical training
Technologies
Vivado, Quartus, SystemVerilog, UVM, Verilog, Jenkins, Docker, Git, LSF, ClearCase, Linux
Responsibilities
Develop and maintain methodologies for ASIC/FPGA design, verification, and implementation; Work with design and verification teams to integrate workflows and tools; Improve design flows using FPGA tools; Set up and manage CI/CD pipelines; Provide technical guidance and training on FPGA/ASIC methodology best practices
Seniority
Mid-Senior, hands-on IC
