Graduate Digital Design Engineer
Core
Designing DSP cores and baseband hardware accelerators for next-generation 5G modem IP targeting User Equipment and base stations, including space and satellite infrastructure.
Role type
Junior IC digital design engineer (VLSI)
Builds
5G modem IP for UE and base stations, including LEO/GEO satellite networks
Domain
Telecommunications + VLSI design
Required skills
RTL design (Verilog/SystemVerilog), digital design fundamentals (logic, FSMs, pipelining, timing), synthesis and timing analysis, EDA tools (Synopsys, Cadence, Siemens), testbench debugging
Preferred skills
M.Sc. in Electrical Engineering, signal processing knowledge, scripting (Python/Tcl/Perl)
Technologies
Verilog, SystemVerilog, Synopsys, Cadence, Siemens EDA, Python, Tcl, Perl
Responsibilities
Write and debug RTL for 5G baseband DSP blocks, translate specifications into synthesizable designs, run lint/synthesis/timing analysis, support verification engineers in testbench debugging, participate in design reviews for PPA trade-offs
Seniority
Junior, recent graduate
