Sr/Staff Digital Design Engineer
Core
Develop RTL modules with DFT considerations for IC development, debug complex logic and mixed-signal simulations, and integrate silicon photonic communication and compute technology into digital accelerator design.
Role type
Sr/Staff Digital Design Engineer (ASIC)
Builds
ASICs for next-generation AI computing architecture
Domain
Semiconductor / Silicon Photonics / AI Infrastructure
Deliverable
production ML models
Required skills
SystemVerilog, Verilog, ASIC design, mixed-signal simulation debugging, advanced semiconductor process nodes, Python scripting, risk management
Preferred skills
PCIe protocols, processor design, memory hierarchies, silicon photonics exposure, analog mixed-signal IP interfacing
Technologies
Synopsys VCS, Cadence Xcelium, Questa
Responsibilities
Develop RTL modules with DFT considerations; Debug complex logic and mixed signal simulations; Integrate silicon photonic communication and compute technology; Collaborate with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams; Create design specifications and documentation; Manage RTL implementation to achieve functionally correct, performant designs.
Seniority
Sr/Staff, hands-on IC
