Digital Design Engineer
Core
Design and develop synthesizable models for FPGA vendor library cells and DSP decomposition models for arithmetic blocks to support static and formal functional verification flows.
Role type
Digital Design Engineer (FPGA modeling & verification)
Builds
Synthesizable FPGA library cells, DSP decomposition models, and verification test harnesses
Domain
Electronic Design Automation (EDA) / FPGA / Hardware Verification
Deliverable
production ML models
Required skills
RTL design fundamentals, Hardware Description Languages (Verilog, VHDL, SystemVerilog), FPGA design flows, P&R tools, Scripting (Shell, Perl, Python), Defect triage
Preferred skills
Siemens EDA tools (simulation, emulation, formal verification), AI agents for cell modeling
Technologies
Vivado, Quartus, Python, Shell, Perl
Responsibilities
Design synthesizable models for FPGA vendor library cells, Develop DSP decomposition models for arithmetic blocks, Integrate new versions from FPGA vendors, Develop and maintain build and regression pipelines, Perform integration testing with upstream tools, Fix and validate defects related to FPGA modeling
Seniority
Mid-level IC Engineer
