Sr/Staff Digital Design Engineer
Core
Develop RTL modules with DFT considerations for an ASIC in next-generation AI computing architecture.
Role type
Senior IC digital design engineer (ASIC)
Builds
High-performance, low-power digital accelerators for optical computing
Domain
Semiconductor / AI data center infrastructure
Deliverable
production ML models
Required skills
SystemVerilog, Verilog, RTL design, DFT, mixed-signal simulation debugging, advanced process node design, Python scripting, risk management
Preferred skills
PCIe protocols, processor design, memory hierarchies, silicon photonics integration, analog mixed-signal IP interfacing
Technologies
Synopsys VCS, Cadence Xcelium, Questa
Responsibilities
Develop RTL modules with DFT considerations; Debug complex logic and mixed signal simulations; Integrate silicon photonic communication and compute technology; Collaborate with Architecture, Verification, Physical Design, Photonic, Analog, and Software teams; Create design specifications and documentation; Manage RTL implementation to achieve performant designs within project schedules
Seniority
Senior, hands-on IC
