Staff Engineer - CPU Design, RTL Development
Core
Design and optimize high-performance CPU and SoC blocks from microarchitecture through RTL and physical implementation.
Role type
Staff IC CPU/SoC Design Engineer
Builds
High-performance, low-power CPU and SoC blocks
Domain
Semiconductor / CPU Architecture / RTL Design
Required skills
Verilog, SystemVerilog, Digital Design, ASIC Development Flows, Python, Tcl, Perl, Shell Scripting, Static Timing Analysis, PPA Optimization, Linux/Unix
Preferred skills
CPU Pipeline Architecture, Out-of-Order Execution, Memory Hierarchy, Microarchitecture, CDC, Formal Verification, Low-Power Design, Floorplanning, Placement, CTS, Routing, Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, MMMC, IR Drop, EM, Signal Integrity, UPF
Technologies
Linux, Perl, Python, SystemVerilog, Unix, Verilog, NodeJS
Responsibilities
Develop and refine Verilog/SystemVerilog RTL; Contribute to microarchitecture definition and PPA trade-offs; Coordinate with physical design teams on synthesis, floorplanning, placement, CTS, routing, and timing closure; Investigate and resolve timing, congestion, power, and area issues; Perform STA/MMMC analysis and timing optimization; Partner with verification teams on functional verification and debugging; Create automation solutions using scripting languages; Mentor junior engineers and improve design methodologies.
Seniority
Staff, hands-on IC with technical leadership
