Physical Design and CAD Engineer
Core
Technical Lead developing next-generation connectivity ASICs for cloud and AI infrastructure, combining Physical Design CAD methodology development with hands-on place-and-route implementation.
Role type
Senior IC Physical Design & CAD Engineer
Builds
Automated design flows and connectivity ASICs for hyperscalers
Domain
Semiconductor / ASIC Physical Design / AI Infrastructure
Deliverable
production ML models
Required skills
Physical Design CAD flows, Place-and-Route (PNR), Timing closure, Python scripting, Tcl scripting, EDA tool flows, Advanced process nodes (7nm+)
Preferred skills
3nm+ process technologies, Automated CAD flows from synthesis to signoff, EM/IR analysis, DRC/LVS, Block-level tapeout ownership
Technologies
Cadence Innovus, Tempus, Genus, Synopsys ICC2, Fusion Compiler, PrimeTime
Responsibilities
Develop and maintain Physical Design CAD flows for advanced nodes; Build automation frameworks using Python/Tcl; Perform hands-on PNR including floorplanning, placement, CTS, routing; Optimize EDA tool flows for timing and verification; Support block-level implementation to GDSII signoff; Collaborate with cross-functional teams for ASIC tapeout.
Seniority
Senior, hands-on IC
