Director of Analog Design – Wearable SoCs (On-site. West Lafayette, USA)
Core
Architect next-generation Wi-R SoCs integrating analog/RF front-end, ultra-low-power digital blocks, and sensor interfaces for brain-inspired wearable computing.
Role type
Director of Analog Design (SoC Architecture & Team Leadership)
Builds
Next-gen Wi-R SoCs (silicon chips) for wearable and implantable devices
Domain
Deep tech / Wearable electronics / Low-power wireless communication
Deliverable
production ML models | product features | infrastructure
Required skills
ASIC/SoC design, mixed-signal/RF architecture, team leadership, RTL-to-GDS flow, IP integration, ESD, packaging co-design, verification methodologies, system-level optimization
Preferred skills
Wearable/bioelectronics/medical device experience, low-power wireless PHYs (Bluetooth/NFC/UWB)
Technologies
Cadence toolchains, floorplanning, DFT, timing closure
Responsibilities
Architect Wi-R SoCs, lead IC design teams, own chip tape-outs end-to-end, define verification methodologies, partner with product/firmware teams, represent silicon to investors/partners
Seniority
Director, hands-on IC design with team leadership
