芯片后端设计工程师（芯片平台） - 芯片研发
Core
End-to-end backend design for CPU/ASIC chips from Netlist to GDSII, including signoff (APR, PV, STA, IR) and supporting tape-out, packaging, and mass production.
Role type
Senior IC backend design engineer (CPU/ASIC)
Builds
CPU/ASIC chips across multiple process nodes and foundries
Domain
Semiconductor / Chip Design
Required skills
RTL-to-GDSII flow, Signoff (APR, PV, STA, IR), Tape-out management, Process integration, Scripting (TCL, Perl, Python), Advanced process nodes (16nm/12nm/7nm)
Preferred skills
Early project evaluation, Planning and project initiation
Technologies
EDA tools for backend, TCL, Perl, Python
Responsibilities
Perform signoff checks (APR, PV, STA, IR) for CPU/ASIC designs, Coordinate tape-out, packaging, and mass production activities, Evaluate and plan potential new projects
Seniority
Mid-level, hands-on IC
