芯片综合/STA工程师（存算与AI） - 芯片研发
Core
Synthesize RTL, perform formal verification, power checks, and sign-off for SoC chips targeting AI large model applications to break memory wall bottlenecks.
Role type
Senior IC chip synthesis and static timing analysis (STA) engineer
Builds
High-efficiency AI chips based on in-memory computing architecture
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
RTL synthesis, formal verification, power analysis, static timing analysis (STA), clock/reset planning, low-power design, process evaluation, library/memory selection, EDA tool usage (Genus, DC, PT, LEC, CLP), DFT, bus protocols, asynchronous design, IP/IO protocols
Preferred skills
STA flow setup, timing risk assessment, scripting (TCL, Python, Perl)
Technologies
Genus, DC, PT, LEC, CLP, Verilog, SDC, UPF, TCL, Python, Perl
Responsibilities
Perform RTL synthesis, formal verification, power checks, and sign-off; Analyze complex timing and clock structures; Collaborate on clock/reset and low-power solutions; Evaluate and select complex processes, libraries, and memories; Define STA sign-off standards and ensure convergence
