Senior SoC Digital Design Engineer, Multimedia Lab
Core
Design hardware accelerators for advanced video encoding and processing within scalable video codec solutions (FPGA and ASIC).
Role type
Senior IC digital design engineer (SoC/Multimedia)
Builds
Video codec hardware accelerators and SoC subsystems
Domain
Semiconductor / Video Processing
Deliverable
production ML models
Required skills
Verilog/SystemVerilog, Digital circuit design, Front-end EDA tools (Spyglass, Design Compiler, PrimeTime), Scripting (Python/Perl/Tcl/Makefile), PPA evaluation, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Low-power design (Clock Gating, Power Gating, UPF)
Preferred skills
NPU architecture, HW/SW co-design, SoC performance profiling, Complex SoC core subsystem integration, Advanced process node tape-out (7nm/5nm/3nm)
Responsibilities
Define SoC architecture and conduct PPA evaluation; Write and maintain RTL code; Perform lint, CDC, and RDC checks; Collaborate with verification and backend teams for debugging and optimization; Formulate and apply low-power design strategies
Seniority
Senior, hands-on IC
